SLVSE72A September 2017  – September 2017 TPS565208

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Adaptive On-Time Control and PWM Operation
      2. 7.3.2Soft Start and Pre-Biased Soft Start
      3. 7.3.3Current Protection
      4. 7.3.4Undervoltage Lockout (UVLO) Protection
      5. 7.3.5Thermal Shutdown
    4. 7.4Device Functional Modes
      1. 7.4.1Normal Operation
      2. 7.4.2Standby Operation
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
        1. 8.2.2.1Custom Design With WEBENCH® Tools
        2. 8.2.2.2Output Voltage Resistors Selection
        3. 8.2.2.3Output Filter Selection
        4. 8.2.2.4Input Capacitor Selection
        5. 8.2.2.5Bootstrap Capacitor Selection
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Development Support
      1. 11.1.1Custom Design With WEBENCH® Tools
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The device is a typical step-down DC-DC converter for converting a higher dc voltage to a lower dc voltage with a maximum available output current of 5 A. The following design procedure can be used to select component values for the TPS565208. Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.

Typical Application

The application schematic in Figure 14 shows the TPS565208 4.5-V to 17-V input, 1.05-V output converter design meeting the requirements for 5-A output. This circuit is available as the evaluation module (EVM). The sections provide the design procedure.

Figure 14. TPS565208 1.05-V, 5-A Reference Design

Design Requirements

Table 1 shows the design parameters for this application.

Table 1. Design Parameters

PARAMETEREXAMPLE VALUE
Input voltage range4.5 to 17 V
Output voltage1.05 V
Transient response, 1A/us slew rateΔVout = ±5%
Input ripple voltage400 mV
Output ripple voltage20 mV
Output current rating5 A
Operating frequency550 kHz

Detailed Design Procedure

Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS565208 device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance
  • Run thermal simulations to understand board thermal performance
  • Export customized schematic and layout into popular CAD formats
  • Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1% tolerance or better divider resistors. Start by using to calculate VOUT.

To improve efficiency at very light loads consider using larger value resistors. However, using too high of resistance causes the circuit to be more susceptible to noise; and, voltage errors from the VFB input current will be more noticeable.

Equation 1. TPS565208 Eq_Vout_SLVSDJ7.gif

Output Filter Selection

The LC filter used as the output filter has double pole at:

Equation 2. TPS565208 Eq_03_SLVSD90.gif

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of Equation 2 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.

Table 2. Recommended Component Values

OUTPUT VOLTAGE (V)R1 (kΩ)R2 (kΩ)L1 (µH)C8 + C9 (µF)
MINTYP MAX
13.0910.012.24.720 to 68
1.053.7410.012.24.720 to 68
1.25.7610.012.24.720 to 68
1.59.5310.01.52.24.720 to 68
1.813.710.01.52.24.720 to 68
2.522.610.02.22.24.720 to 68
3.333.210.02.22.24.720 to 68
554.910.03.33.34.720 to 68
6.57510.03.33.34.720 to 68

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 3, Equation 4, and Equation 5. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current.

Use 550 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 4 and the RMS current of Equation 6.

Equation 3.
Equation 4. TPS565208 Eq_Ipeak2_SLVSE72.gif
Equation 5. TPS565208 Eq_ILorms2_SLVSE72.gif

For this design example, the calculated peak current is 5.4 A and the calculated RMS current is 5 A. The inductor used is a WE 744311220 with a peak current rating of 13 A and an RMS current rating of 9 A.

The capacitor value and ESR determines the amount of output voltage ripple. The TPS565208 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 6 to determine the required RMS current rating for the output capacitor.

Equation 6. TPS565208 Eq_07_SLVSD90.gif

For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.229 A.

Input Capacitor Selection

The TPS565208 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage rating needs to be greater than the maximum input voltage.

Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI recommends to use a ceramic capacitor.

Application Curves

TPS565208 D015_SLVSE72.gif
VIN = 5 V VOUT1 = 1.05 V
Figure 15. TPS565208 Load Regulation, VIN = 5 V
TPS565208 D017_SLVSE72.gif
IOUT = 1 A
Figure 17. TPS565208 Line Regulation
TPS565208 Figure 19. Input Voltage Ripple.png
1 µs/div
Figure 19. TPS565208 Input Voltage Ripple
TPS565208 Output_Voltage_Ripple_IOUT_2p5A_21_SLVSE71.gif
1 µs/div
Figure 21. TPS565208 Output Voltage Ripple, IOUT 2.5 A
TPS565208 Load_Transient_Response_0p1A_to_2p5A_23_SLVSE72.gif
100 µs/div
Figure 23. TPS565208 Transient Response 0.1 to 2.5 A
TPS565208 Load_Transient_Response_2p5A_to_5A_25_SLVSE72.gif
100 µs/div
Figure 25. TPS565208 Transient Response, 2.5 to 5 A
TPS565208 Start-up_Relative_to_EN_27_SLVSE71.gif
400 µs/div
Figure 27. TPS565208 Startup Relative to EN
TPS565208 Shut-Down_Relative_to_EN_29_SLVSE71.gif
400 µs/div
Figure 29. TPS565208 Shutdown Relative to EN
TPS565208 D016_SLVSE72.gif
VIN = 12 V VOUT1 = 1.05 V
Figure 16. TPS565208 Load Regulation, VIN = 12 V
TPS565208 D009_SLVSE72.gif
Figure 18. TPS565208 Efficiency, Vout = 1.05 V
TPS565208 Figure 20. Output Voltage Ripple, no load.png
1 µs/div
Figure 20. TPS565208 Output Voltage Ripple, No Load
TPS565208 Output_Voltage_Ripple_IOUT_5A_22_SLVSE71.gif
1 µs/div
Figure 22. TPS565208 Output Voltage Ripple, IOUT 5 A
TPS565208 Load_Transient_Response_1p25A_to_3p75A_24_SLVSE71.gif
100 µs/div
Figure 24. TPS565208 Transient Response, 1.25 to 3.75 A
TPS565208 Start-up_Relative_to_VIN_26_SLVSE71.gif
2 ms/div
Figure 26. TPS565208 Startup Relative to VIN
TPS565208 Shut-Down_Relative_to_VIN_28_SLVSE71.gif
20 ms/div
Figure 28. TPS565208 Shutdown Relative to VIN