SLVSE72A September 2017  – September 2017 TPS565208


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Adaptive On-Time Control and PWM Operation
      2. 7.3.2Soft Start and Pre-Biased Soft Start
      3. 7.3.3Current Protection
      4. 7.3.4Undervoltage Lockout (UVLO) Protection
      5. 7.3.5Thermal Shutdown
    4. 7.4Device Functional Modes
      1. 7.4.1Normal Operation
      2. 7.4.2Standby Operation
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
        1. Design With WEBENCH® Tools
        2. Voltage Resistors Selection
        3. Filter Selection
        4. Capacitor Selection
        5. Capacitor Selection
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Development Support
      1. 11.1.1Custom Design With WEBENCH® Tools
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Detailed Description


The TPS564208 is a 5-A synchronous step-down converter. The proprietary D-CAP2™ mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP2™ mode control can reduce the output capacitance required to meet a specific level of performance.

Functional Block Diagram

TPS565208 block_diagramv2_SLVSE71.gif

Feature Description

Adaptive On-Time Control and PWM Operation

The main control loop of the TPS565208 is adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with low-ESR ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one-shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN, and proportional to the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An ripple is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2TM mode control.

Soft Start and Pre-Biased Soft Start

The TPS565208 has an internal 1.0-ms soft-start. When the EN pin becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.

If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the converter ramps up smoothly into regulation point.

Current Protection

The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The inductor current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN, VOUT, and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.

There are some important considerations for this type of over-current protection. The load current is higher than the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP threshold voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time (typically 24 µs) and re-starts after the hiccup time (typically 14.9 ms).

When the over current condition is removed, the output voltage returns to the regulated value.

Undervoltage Lockout (UVLO) Protection

UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.

Thermal Shutdown

The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C), the device is shut off. This is a non-latch protection.

Device Functional Modes

Normal Operation

When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS565208 operates in the normal switching mode. Normal continuous conduction mode (CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS565208 operates at a quasi-fixed frequency of 550 kHz.

Standby Operation

When the TPS565208 is operating in normal CCM, it may be placed in standby by asserting the EN pin low.