SLVSDY9 March 2017 TPS65263-1Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 Adjusting the Output Voltage
      2. 7.3.2 Enable and Adjusting UVLO
      3. 7.3.3 Soft-Start Time
      4. 7.3.4 Power-Up Sequencing
      5. 7.3.5 V7V Low-Dropout Regulator and Bootstrap
      6. 7.3.6 Out-of-Phase Operation
      7. 7.3.7 Output Overvoltage Protection (OVP)
      8. 7.3.8 PSM
      9. 7.3.9 Slope Compensation
      10. 7.3.10Overcurrent Protection
        1. MOSFET Overcurrent Protection
        2. MOSFET Overcurrent Protection
      11. 7.3.11Power Good
        1. Switching Frequency
      12. 7.3.12Thermal Shutdown
    4. 7.4Device Functional Modes
      1. 7.4.1Serial Interface Description
      2. 7.4.2I2C Update Sequence
    5. 7.5Register Maps
      1. 7.5.1VOUT2_SEL: Vout2 Voltage Selection Register (Address = 0x01H)
      2. 7.5.2VOUT1_COM: Buck1 Command Register (offset = 0x03H)
      3. 7.5.3VOUT2_COM: Buck2 Command Register (offset = 0x04H)
      4. 7.5.4VOUT3_COM: Buck3 Command Register (offset = 0x05H)
      5. 7.5.5SYS_STATUS: System Status Register (offset = 0x06H)
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
        1. Inductor Selection
        2. Capacitor Selection
        3. Capacitor Selection
        4. Compensation
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Receiving Notification of Documentation Updates
    2. 11.2Community Resources
    3. 11.3Trademarks
    4. 11.4Electrostatic Discharge Caution
    5. 11.5Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information


  • Qualified for Automotive Applications
  • AEC-Q100 Qualification With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Operating Junction Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C4B
  • Operating Input Voltage Range 4.0- to 18-V Maximum Continuous Output Current 3 A/2 A/2 A
  • I2C Controlled 7-Bits VID Programmable Output Voltage from 0.68 to 1.95 V With 10-mV Voltage Step for Buck2
  • I2C Controlled VID Voltage Transition Slew Rate for Buck2
  • I2C Read Back Power Good Status, Overcurrent Warning and Die Temperature Warning
  • I2C Compatible Interface With Standard Mode (100 kHz) and Fast Mode (400 kHz)
  • Feedback Reference Voltage 0.6 V ±1%
  • Adjustable Clock Frequency from 200 kHz to 2.3 MHz
  • FCC Mode (Default)
  • External Clock Synchronization
  • Dedicated Enable and Soft-Start Pins for Each Buck
  • Output Voltage Power Good Indicator
  • Thermal Overloading Protection


  • Automotive
  • Car Audio/Video
  • Home Gateway and Access Point Networks
  • Surveillance


The TPS65263-1Q1 incorporates triple-synchronous buck converters with 4.0- to 18-V wide input voltage. The converter with constant frequency peak current mode is designed to simplify its application while giving designers options to optimize the system according to targeted applications. The switching frequency of the converters is adjustable from 200 kHz to 2.3 MHz with an external resistor. 180° out-of-phase operation between buck1 and buck2, buck3 (buck2 and buck3 run in phase) minimizes the input filter requirements.

The initial startup voltage of each buck can be set with external feedback resistors. The output voltage of buck2 can be dynamically scaled from 0.68 to 1.95 V in 10-mV steps with I2C-controlled 7 bits VID. The VID voltage transition slew rate is programmable with 3-bits control through I2C bus to optimize overshoot/undershoot during VID voltage transition.

Each buck in TPS65263-1Q1 can be I2C controlled for enabling/disabling output voltage, setting the pulse skipping mode (PSM) or forced continuous current (FCC) mode at light load condition and reading the power-good status, overcurrent warning, and die temperature warning.

The TPS65263-1Q1 features overvoltage, overcurrent, short-circuit, and overtemperature protection.

Device Information(1)

TPS65263-1Q1VQFN (32)5.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Application Schematic

TPS65263-1Q1 typ_app_pg_1_slvsdy9.gif

Efficiency vs Output Load

TPS65263-1Q1 D022_SLVSDY9.gif