SLVSD93A October 2015  – April 2016 TPS65983

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Power Supply Requirements and Characteristics
    6. 7.6 Power Supervisor Characteristics
    7. 7.7 Power Consumption Characteristics
    8. 7.8 Cable Detection Characteristics
    9. 7.9 USB-PD Baseband Signal Requirements and Characteristics
    10. 7.10USB-PD TX Driver Voltage Adjustment Parameter
    11. 7.11Port Power Switch Characteristics
    12. 7.12Port Data Multiplexer Switching and Timing Characteristics
    13. 7.13Port Data Multiplexer Clamp Characteristics
    14. 7.14Port Data Multiplexer SBU Detection Requirements
    15. 7.15Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
    16. 7.16Port Data Multiplexer USB Endpoint Requirements and Characteristics
    17. 7.17Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
    18. 7.18Analog-to-Digital Converter (ADC) Characteristics
    19. 7.19Input/Output (I/O) Requirements and Characteristics
    20. 7.20I2C Slave Requirements and Characteristics
    21. 7.21SPI Master Characteristics
    22. 7.22Single-Wire Debugger (SWD) Timing Requirements
    23. 7.23BUSPOWERZ Configuration Requirements
    24. 7.24HPD Timing Requirements and Characteristics
    25. 7.25Thermal Shutdown Characteristics
    26. 7.26Oscillator Requirements and Characteristics
    27. 7.27Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 USB-PD Physical Layer
        1. 9.3.1.1USB-PD Encoding and Signaling
        2. 9.3.1.2USB-PD Bi-Phase Marked Coding
        3. 9.3.1.3USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.1.4USB-PD BMC Transmitter
        5. 9.3.1.5USB-PD BMC Receiver
      2. 9.3.2 Cable Plug and Orientation Detection
        1. 9.3.2.1Configured as a DFP
        2. 9.3.2.2Configured as a UFP
        3. 9.3.2.3Dead-Battery or No-Battery Support
      3. 9.3.3 Port Power Switches
        1. 9.3.3.1 5V Power Delivery
        2. 9.3.3.2 5V Power Switch as a Source
        3. 9.3.3.3 PP_5V0 Current Sense
        4. 9.3.3.4 PP_5V0 Current Limit
        5. 9.3.3.5 Internal HV Power Delivery
        6. 9.3.3.6 Internal HV Power Switch as a Source
        7. 9.3.3.7 Internal HV Power Switch as a Sink
        8. 9.3.3.8 Internal HV Power Switch Current Sense
        9. 9.3.3.9 Internal HV Power Switch Current Limit
        10. 9.3.3.10External HV Power Delivery
        11. 9.3.3.11External HV Power Switch as a Source with RSENSE
        12. 9.3.3.12External HV Power Switch as a Sink with RSENSE
        13. 9.3.3.13External HV Power Switch as a Sink without RSENSE
        14. 9.3.3.14External Current Sense
        15. 9.3.3.15External Current Limit
        16. 9.3.3.16Soft Start
        17. 9.3.3.17BUSPOWERZ
        18. 9.3.3.18Voltage Transitions on VBUS through Port Power Switches
        19. 9.3.3.19HV Transition to PP_RV0 Pull-Down on VBUS
        20. 9.3.3.20VBUS Transition to VSAVE0V
        21. 9.3.3.21C_CC1 and C_CC2 Power Configuration and Power Delivery
        22. 9.3.3.22PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        23. 9.3.3.23PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 9.3.4 USB Type-C Port Data Multiplexer
        1. 9.3.4.1 USB Top and Bottom Ports
        2. 9.3.4.2 Multiplexer Connection Orientation
        3. 9.3.4.3 Digital Crossbar Multiplexer
        4. 9.3.4.4 SBU Crossbar Multiplexer
        5. 9.3.4.5 Signal Monitoring and Pullup and Pulldown
        6. 9.3.4.6 Port Multiplexer Clamp
        7. 9.3.4.7 USB2.0 Low-Speed Endpoint
        8. 9.3.4.8 Battery Charger (BC1.2) Detection Block
        9. 9.3.4.9 BC1.2 Data Contact Detect
        10. 9.3.4.10BC1.2 Primary and Secondary Detection
      5. 9.3.5 Power Management
        1. 9.3.5.1Power-On and Supervisory Functions
        2. 9.3.5.2Supply Switch-Over
        3. 9.3.5.3RESETZ and MRESET
      6. 9.3.6 Digital Core
      7. 9.3.7 USB-PD BMC Modem Interface
      8. 9.3.8 System Glue Logic
      9. 9.3.9 Power Reset Congrol Module (PRCM)
      10. 9.3.10Interrupt Monitor
      11. 9.3.11ADC Sense
      12. 9.3.12UART
      13. 9.3.13I2C Slave
      14. 9.3.14SPI Master
      15. 9.3.15Single-Wire Debugger Interface
      16. 9.3.16DisplayPort HPD Timers
      17. 9.3.17ADC
        1. 9.3.17.1ADC Divider Ratios
        2. 9.3.17.2ADC Operating Modes
        3. 9.3.17.3Single Channel Readout
        4. 9.3.17.4Round Robin Automatic Readout
        5. 9.3.17.5One Time Automatic Readout
      18. 9.3.18I/O Buffers
        1. 9.3.18.1IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 9.3.18.2IOBUF_OD
        3. 9.3.18.3IOBUF_UTX
        4. 9.3.18.4IOBUF_URX
        5. 9.3.18.5IOBUF_PORT
        6. 9.3.18.6IOBUF_I2C
        7. 9.3.18.7IOBUF_GPIOHSPI
        8. 9.3.18.8IOBUF_GPIOHSSWD
      19. 9.3.19Thermal Shutdown
      20. 9.3.20Oscillators
    4. 9.4Device Functional Modes
      1. 9.4.1Boot Code
      2. 9.4.2Initialization
      3. 9.4.3I2C Configuration
      4. 9.4.4Dead-Battery Condition
      5. 9.4.5Application Code
      6. 9.4.6Flash Memory Read
      7. 9.4.7Invalid Flash Memory
      8. 9.4.8UART Download
        1. 9.4.8.1Primary TPS65983 Flash Master and Secondary Port
    5. 9.5Programming
      1. 9.5.1SPI Master Interface
      2. 9.5.2I2C Slave Interface
        1. 9.5.2.1I2C Interface Description
        2. 9.5.2.2I2C Clock Stretching
        3. 9.5.2.3I2C Address Setting
        4. 9.5.2.4Unique Address Interface
        5. 9.5.2.5I2C Pin Address Setting
  10. 10Application and Implementation
    1. 10.1Application Information
    2. 10.2Typical Application
      1. 10.2.1Fully-Featured USB Type-C and PD Charger Application
        1. 10.2.1.1Design Requirements
          1. 10.2.1.1.1External FET Path Components (PP_EXT and RSENSE)
        2. 10.2.1.2Detailed Design Procedure
          1. 10.2.1.2.1TPS65983 External Flash
          2. 10.2.1.2.2I2C (I2C), Debug Control (DEBUG_CTL), and Single-Wire De-bugger (SWD) Resistors
          3. 10.2.1.2.3Oscillator (R_OSC) Resistor
          4. 10.2.1.2.4VBUS Capacitor and Ferrite Bead
          5. 10.2.1.2.5Soft Start (SS) Capacitor
          6. 10.2.1.2.6USB Top (C_USB_T), USB Bottom (C_USB_B), and Sideband-Use (SBU) Connections
          7. 10.2.1.2.7Port Power Switch (PP_EXT, PP_HV, PP_5V0, and PP_CABLE) Capacitors
          8. 10.2.1.2.8Cable Connection (CCn) Capacitors and RPD_Gn Connections
          9. 10.2.1.2.9LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
        3. 10.2.1.3Application Curve
  11. 11Power Supply Recommendations
    1. 11.13.3 V Power
      1. 11.1.11VIN_3V3 Input Switch
      2. 11.1.2VOUT_3V3 Output Switch
      3. 11.1.3VBUS 3.3 V LDO
    2. 11.21.8 V Core Power
      1. 11.2.11.8 V Digital LDO
      2. 11.2.21.8 V Analog LDO
    3. 11.3VDDIO
      1. 11.3.1Recommended Supply Load Capacitance
      2. 11.3.2Schottky for Current Surge Protection
  12. 12Layout
    1. 12.1Layout Guidelines
      1. 12.1.1 TPS65983 Recommended Footprints
        1. 12.1.1.1Standard TPS65983 Footprint (Circular Pads)
      2. 12.1.2 Alternate TPS65983 Footprint (Oval Pads)
      3. 12.1.3 Top TPS65983 Placement and Bottom Component Placement and Layout
      4. 12.1.4 Oval Pad Footprint Layout and Placement
      5. 12.1.5 Component Placement
      6. 12.1.6 Designs Rules and Guidance
      7. 12.1.7 Routing PP_HV, PP_EXT, PP_5V0, and VBUS
      8. 12.1.8 Routing Top and Bottom Passive Components
      9. 12.1.9 Void Via Placement
      10. 12.1.10Top Layer Routing
      11. 12.1.11Inner Signal Layer Routing
      12. 12.1.12Bottom Layer Routing
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Device Support
    2. 13.2Documentation Support
      1. 13.2.1Related Documentation
    3. 13.3Community Resources
    4. 13.4Trademarks
    5. 13.5Electrostatic Discharge Caution
    6. 13.6Glossary
  14. 14Mechanical, Packaging, and Orderable Information

1 Features

  • USB Power Delivery (PD) Controller
    • Mode Configuration for Source (Host), Sink (Device), or Source-Sink
    • Bi-Phase Marked Encoding/Decoding (BMC)
    • Physical Layer (PHY) Protocol
    • Policy Engine
    • Configurable at Boot and Host-Controlled
  • USB Type-C Specification Compliant
    • Detect USB Cable Plug Attach
    • Cable Orientation and Role Detection
    • Assign CC and VCONN Pins
    • Advertise Default, 1.5 A or 3 A for Type-C Power
  • Port Power Switch
    • 5-V, 3-A Switch to VBUS for Type-C Power
    • 5-V to 20-V, 3-A Bidirectional Switch to or from VBUS for USB PD Power
    • 5-V, 600-mA Switches for VCONN
    • Overcurrent Limiter, Overvoltage Protector
    • Slew Rate Control
    • Hard Reset Support
  • Port Data Multiplexer
    • USB 2.0 HS Data, UART Data, and Low Speed Endpoint
    • Sideband Use Data for Alternate Modes (DisplayPort and Thunderbolt™)
  • Power Management
    • Gate Control and Current Sense for External 5-V to 20-V, 5-A Bidirectional Switch (Back-to-Back NFETs)
    • Power Supply from 3.3-V or VBUS Source
    • 3.3-V LDO Output for Dead Battery Support
  • BGA MicroStar Junior Package
    • 0.5-mm Pitch
    • Through-Hole Via Compatible for All Pins

2 Applications

  • Thunderbolt 3 Devices

3 Description

The TPS65983 is a stand-alone USB Type-C and Power Delivery (PD) controller providing cable plug and orientation detection at the USB Type-C connector. Upon cable detection, the TPS65983 communicates on the CC wire using the USB PD protocol. When cable detection and USB PD negotiation are complete, the TPS65983 enables the appropriate power path and configures alternate mode settings for internal and (optional) external multiplexers.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
TPS65983BGA MICROSTAR JUNIOR (96)6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Diagram

TPS65983 pg1_slvsd93.gif