The TPS779xx is a low-dropout regulator with integrated power-on reset. The device is capable of supplying 250 mA of output current with a dropout of 200 mV (TPS77930). Quiescent current is 92 uA at full load dropping down to 1 uA when the device is disabled. The device is optimized to be stable with a wide range of output capacitors including low ESR ceramic (10uF) or low capacitance (1uF) tantalum capacitors. The device has extremely low noise output performance (55 uVrms) without using any added filter capacitors. TPS779xx is designed to have a fast transient response for larger load current changes.
The TPS779xx is offered in 1.8-V, 2.5-V, and 3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The TPS779xx family is available in 8-pin MSOP (DGK) packages.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 200 mV at an output current of 250 mA for 3.3 volt option) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 92 uA over the full range of output current, 0 mA to 250 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The device is enabled when the EN pin is connected to a high-level input voltage. This LDO family also features a sleep mode; applying a TTL low signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 uA at TJ = 25°C.
The TPS779xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS), or reset output voltage. The RESET\ output of the TPS779xx initiates a reset in DSP, microcomputer, or microprocessor systems at power-up and in the event of an undervoltage condition. An internal comparator in the TPS779xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT reaches 95% of its regulated voltage, RESET\ will go to a high-impedance state after a 220 ms delay. RESET\ will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition) of its regulated voltage.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | 250-mA LDO Regulator with Integrated Reset in a MSOP8 Package datasheet (Rev. D) | 22 Mar 2002 | |
| Application note | LDO Noise Demystified (Rev. B) | PDF | HTML | 18 Aug 2020 | |
| Application note | LDO PSRR Measurement Simplified (Rev. A) | PDF | HTML | 09 Aug 2017 | |
| Application note | Ceramic Capacitors Replace Tantalum Capacitors in LDOs (Rev. A) | 13 Oct 2006 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | Download |
|---|---|---|
| VSSOP (DGK) | 8 | View options |
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