SLVSDU9A February 2017 – March 2017
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS7B63xx-Q1 device is a 300-mA low-dropout watchdog linear regulator with ultralow quiescent current. The PSpice transient model is available for download on the product folder and can be used to evaluate the basic function of the device.
Figure 26 shows a typical application circuit for the TPS7B63xx-Q1 device. Different values of external components can be used, depending on the end application. An application may require a larger output capacitor during fast load steps to prevent a large drop on the output voltage. TI recommends using a low-ESR ceramic capacitor with a dielectric of type X7R.
For this design example, use the parameters listed in Table 3.
|DESIGN PARAMETER||EXAMPLE VALUES|
|Input voltage range||4 V to 40 V for TPS7B6333-Q1|
5.6 V to 40 V for TPS7B6350-Q1
|Input capacitor range||10 μF to 22 μF|
|Output voltage||3.3 V, 5 V|
|Output current rating||300 mA maximum|
|Output capacitor range||4.7 μF to 500 μF|
|Power-good threshold||Adjustable or fixed|
|Power-good delay capacitor||100 pF to 100 nF|
|Watchdog type||Standard watchdog or window watchdog|
|Watchdog window periods||10 ms to 500 ms|
To begin the design process, determine the following:
When using a TPS7B63xx-Q1 device, TI recommends adding a 10-μF to 22-μF capacitor with a 0.1 μF ceramic bypass capacitor in parallel at the input to keep the input voltage stable. The voltage rating must be greater than the maximum input voltage.
Ensuring the stability of the TPS7B63xx-Q1 device requires an output capacitor with a value in the range from 4.7 μF to 500 μF and with an ESR range from 0.001 Ω to 20 Ω. TI recommends selecting a ceramic capacitor with low ESR to improve the load transient response.
The power-good threshold is set by connecting PGADJ to GND or to a resistor divider from OUT to GND. Adjustable Power-Good Threshold (PG, PGADJ) provides the method for setup of the power-good threshold.
The power-good delay period is set by an external capacitor (CDELAY) to ground, with a typical capacitor value from 100 pF to 100 nF. Calculate the correct capacitance for the application using Equation 2.
The Integrated Watchdog section discusses the watchdog type selection and watchdog window-period setup method.