SLVSDU9A February 2017  – March 2017


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Switching Characteristics
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Device Enable (EN)
      2. 7.3.2Adjustable Power-Good Threshold (PG, PGADJ)
      3. 7.3.3Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4Undervoltage Shutdown
      5. 7.3.5Current Limit
      6. 7.3.6Thermal Shutdown
      7. 7.3.7Integrated Watchdog
        1. Watchdog (WTS, ROSC, FSEL and WRS)
        2. Watchdog (WTS, ROSC and FSEL)
        3. Service Signal and Watchdog Fault Outputs (WD and WDO)
        4. Status Detection (ROSC)
        5. Enable (PG and WD_EN)
        6. Initialization
        7. Watchdog Operation (WTS = Low)
        8. Watchdog Operation (WTS = High)
    4. 7.4Device Functional Modes
      1. 7.4.1Operation With Input Voltage Lower Than 4 V
      2. 7.4.2Operation With Input Voltage Higher Than 4 V
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
        1. Capacitor
        2. Capacitor
        3. Threshold
        4. Delay Period
        5. Setup
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Related Links
    3. 11.3Receiving Notification of Documentation Updates
    4. 11.4Community Resources
    5. 11.5Trademarks
    6. 11.6Electrostatic Discharge Caution
    7. 11.7Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TPS7B63xx-Q1 device is a 300-mA low-dropout watchdog linear regulator with ultralow quiescent current. The PSpice transient model is available for download on the product folder and can be used to evaluate the basic function of the device.

Typical Application

Figure 26 shows a typical application circuit for the TPS7B63xx-Q1 device. Different values of external components can be used, depending on the end application. An application may require a larger output capacitor during fast load steps to prevent a large drop on the output voltage. TI recommends using a low-ESR ceramic capacitor with a dielectric of type X7R.

TPS7B6333-Q1 TPS7B6350-Q1 Typ_app_sch_SLVSDU9.gif Figure 26. TPS7B63xx-Q1 Typical Application Schematic

Design Requirements

For this design example, use the parameters listed in Table 3.

Table 3. Design Parameters

Input voltage range4 V to 40 V for TPS7B6333-Q1
5.6 V to 40 V for TPS7B6350-Q1
Input capacitor range10 μF to 22 μF
Output voltage3.3 V, 5 V
Output current rating300 mA maximum
Output capacitor range4.7 μF to 500 μF
Power-good thresholdAdjustable or fixed
Power-good delay capacitor100 pF to 100 nF
Watchdog typeStandard watchdog or window watchdog
Watchdog window periods10 ms to 500 ms

Detailed Design Procedure

To begin the design process, determine the following:

  • Input voltage range
  • Output voltage
  • Output current
  • Power-good threshold
  • Power-good delay capacitor
  • Watchdog type
  • Watchdog window period

Input Capacitor

When using a TPS7B63xx-Q1 device, TI recommends adding a 10-μF to 22-μF capacitor with a 0.1 μF ceramic bypass capacitor in parallel at the input to keep the input voltage stable. The voltage rating must be greater than the maximum input voltage.

Output Capacitor

Ensuring the stability of the TPS7B63xx-Q1 device requires an output capacitor with a value in the range from 4.7 μF to 500 μF and with an ESR range from 0.001 Ω to 20 Ω. TI recommends selecting a ceramic capacitor with low ESR to improve the load transient response.

Power-Good Threshold

The power-good threshold is set by connecting PGADJ to GND or to a resistor divider from OUT to GND. Adjustable Power-Good Threshold (PG, PGADJ) provides the method for setup of the power-good threshold.

Power-Good Delay Period

The power-good delay period is set by an external capacitor (CDELAY) to ground, with a typical capacitor value from 100 pF to 100 nF. Calculate the correct capacitance for the application using Equation 2.

Watchdog Setup

The Integrated Watchdog section discusses the watchdog type selection and watchdog window-period setup method.

Application Curves

TPS7B6333-Q1 TPS7B6350-Q1 D021_SLVSD43.gif
Figure 27. TPS7B6350-Q1 Power-Up Waveform
TPS7B6333-Q1 TPS7B6350-Q1 D022_SLVSD43.gif
Figure 28. TPS7B6350-Q1 Watchdog Fault (High-Frequency Watchdog Service Signal)