SLVSDU9A February 2017  – March 2017

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Switching Characteristics
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Device Enable (EN)
      2. 7.3.2Adjustable Power-Good Threshold (PG, PGADJ)
      3. 7.3.3Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4Undervoltage Shutdown
      5. 7.3.5Current Limit
      6. 7.3.6Thermal Shutdown
      7. 7.3.7Integrated Watchdog
        1. 7.3.7.1Window Watchdog (WTS, ROSC, FSEL and WRS)
        2. 7.3.7.2Standard Watchdog (WTS, ROSC and FSEL)
        3. 7.3.7.3Watchdog Service Signal and Watchdog Fault Outputs (WD and WDO)
        4. 7.3.7.4ROSC Status Detection (ROSC)
        5. 7.3.7.5Watchdog Enable (PG and WD_EN)
        6. 7.3.7.6Watchdog Initialization
        7. 7.3.7.7Window Watchdog Operation (WTS = Low)
        8. 7.3.7.8Standard Watchdog Operation (WTS = High)
    4. 7.4Device Functional Modes
      1. 7.4.1Operation With Input Voltage Lower Than 4 V
      2. 7.4.2Operation With Input Voltage Higher Than 4 V
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
        1. 8.2.2.1Input Capacitor
        2. 8.2.2.2Output Capacitor
        3. 8.2.2.3Power-Good Threshold
        4. 8.2.2.4Power-Good Delay Period
        5. 8.2.2.5Watchdog Setup
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Related Links
    3. 11.3Receiving Notification of Documentation Updates
    4. 11.4Community Resources
    5. 11.5Trademarks
    6. 11.6Electrostatic Discharge Caution
    7. 11.7Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

Detailed Description

Overview

The TPS7B63xx-Q1 device is a family of 300-mA, 40-V monolithic low-dropout linear voltage regulators with integrated watchdog and adjustable power-good threshold functionality. These voltage regulators consume only 19-µA quiescent current in light-load applications. Because of the adjustable power-good delay (also called power-on-reset delay) and the adjustable power-good threshold, these devices are well-suited as power supplies for microprocessors and microcontrollers in automotive applications.

Functional Block Diagram

TPS7B6333-Q1 TPS7B6350-Q1 fbd_SLVSD43.gif

Feature Description

Device Enable (EN)

The EN pin is a high-voltage-tolerant pin. A high input activates the device and turns the regulator ON. Connect this input pin to an external microcontroller or a digital control circuit to enable and disable the device, or connect to the IN pin for self-bias applications.

Adjustable Power-Good Threshold (PG, PGADJ)

The PG pin is an open-drain output with an external pullup resistor to the regulated supply, and the PGADJ pin is a power-good threshold adjustment pin. Connecting the PGADJ pin to GND sets the power-good threshold value to the default, V(PG_TH). When VOUT exceeds the default power-good threshold, the PG output turns high after the power-good delay period has expired. When VOUT falls below V(PG_TH) – V(PG_HYST), the PG output turns low after a short deglitch time.

The power-good threshold is also adjustable from 1.1 V to 5 V by using an external resistor divider between PGADJ and OUT. The threshold can be calculated using Equation 1:

Equation 1. TPS7B6333-Q1 TPS7B6350-Q1 eq01-Vpgadj_SLVSD43.gif

where

  • V(PG_ADJ) is the adjustable power-good threshold
  • V(PG_REF) is the internal comparator reference voltage of the PGADJ pin, 1.1 V typical, 2% accuracy specified under all conditions

By setting the power-good threshold V(PG_ADJ), when VOUT exceeds this threshold, the PG output turns high after the power-good delay period has expired. When VOUT falls below V(PG_ADJ) – V(PG_HYST), the PG output turns low after a short deglitch time.

TPS7B6333-Q1 TPS7B6350-Q1 adj-pg-thresh_SLVSD43.gif Figure 21. Adjustable Power-Good Threshold

Adjustable Power-Good Delay Timer (DELAY)

The power-good delay period is a function of the value set by an external capacitor on the DELAY pin before turning the PG pin high. Connecting an external capacitor from this pin to GND sets the power-good delay period. The constant current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator, and Equation 2 determines the power-good delay period:

Equation 2. TPS7B6333-Q1 TPS7B6350-Q1 eq02-tDLY_SLVSD43.gif

where

  • t(DLY) is the adjustable power-good delay period
  • CDELAY is the value of the power-good delay capacitor
TPS7B6333-Q1 TPS7B6350-Q1 pg-activ_SLVSD43.gif Figure 22. Power Up and Conditions for Activation of Power Good

If the DELAY pin is open, the default delay time is t(DLY_FIX).

Undervoltage Shutdown

These devices have an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input voltage falls below an internal UVLO threshold, V(UVLO). This ensures that the regulator does not latch into an unknown state during low-input-voltage conditions. If the input voltage has a negative transient which drops below the UVLO threshold and recovers, the regulator shuts down and powers up with a normal power-up sequence once the input voltage is above the required level.

Current Limit

These devices feature current-limit protection to keep the device in a safe operating area when an overload or output short-to-ground condition occurs. This protects devices from excessive power dissipation. For example, during a short-circuit condition on the output, fault protection limits the current through the pass element to I(LIM) to protect the device from excessive power dissipation.

Thermal Shutdown

These devices incorporate a thermal shutdown (TSD) circuit as a protection from overheating. For continuous normal operation, the junction temperature should not exceed the TSD trip point. The junction temperature exceeding the TSD trip point causes the output to turn off. When the junction temperature falls below the T(SD) – T(HYST), the output turns on again.

Integrated Watchdog

These devices have an integrated watchdog with fault (WDO) output option. Both window watchdog and standard watchdog are available in one device. The watchdog operation, service fault conditions, and differences between window watchdog and standard watchdog are described as follows.

Window Watchdog (WTS, ROSC, FSEL and WRS)

These devices work in the window watchdog mode when the watchdog type selection (WTS) pin is connected to a to low voltage level. The user can set the duration of the watchdog window by connecting an external resistor (RROSC) to ground at the ROSC pin and setting the voltage level at the FSEL pin. The current through the RROSC resistor sets the clock frequency of the internal oscillator. The user can adjust the duration of the watchdog window (the watchdog timer period) by changing the resistor value. A high voltage level at the FSEL pin sets the watchdog window duration to 5 times as long as that of a low voltage level with same external component configuration.

The duration of the watchdog window and the duration of the fault output are multiples of the internal oscillator frequency, as shown by the following equations:

FSEL low
Equation 3. t(WD) = RROSC × 0.5 × 10-6
FSEL high
Equation 4. t(WD) = RROSC × 2.5 × 10-6
Watchdog initialization
Equation 5. t(WD_INI) = 8 × t(WD)
Open and closed windows
Equation 6. t(WD) = t(OW) + t(CW)
WRS low
Equation 7. t(OW) = t(CW) = 50% × t(WD)
WRS high
Equation 8. t(OW) = 8 × t(CW) = (8 / 9) × t(WD)

where:

  • t(WD) is the duration of the watchdog window
  • RROSC is the resistor connected at the ROSC pin
  • t(WD_INI) is the duration of the watchdog initialization
  • t(OW) is the duration of the open watchdog window
  • t(CW) is the duration of the closed watchdog window

For all the foregoing items, the unit of resistance is Ω and the unit of time is s.

Table 1 illustrates several periods of watchdog window with typical conditions.

Table 1. Several Typical Periods of Watchdog Window

FSELR(ROSC) (kΩ)I(ROSC) (µA)t(WD) (ms)WATCHDOG PERIOD TOLERANCE
High200550015%
1001025010%
5020125
4025100
254062.5
205050
Low100105010%
502025
402520
254012.5
205010

As shown in Figure 23, each watchdog window consists of an open window and a closed window. While the window ratio selection (WRS) pin is low, each open window (t(OW)) and closed window (t(CW)) has a width approximately 50% of the watchdog window (t(WD)). While the WRS pin is high, the ratio between open window and closed window is about 8:1. However, there is an exception to this; the first open window after watchdog initialization (t(WD_INI)) is eight times the duration of the watchdog window. The watchdog must receive the service signal (by software, external microcontroller, and so forth) during this initialization open window.

A watchdog fault occurs when servicing the watchdog during a closed window, or not servicing during an open window.

TPS7B6333-Q1 TPS7B6350-Q1 wd-init_SLVSD43.gif Figure 23. Watchdog Initialization, Open Window and Closed Window

Standard Watchdog (WTS, ROSC and FSEL)

These devices work in the standard watchdog mode when the watchdog type selection (WTS) pin is connected to a high voltage level. The same as in window watchdog mode, the user can set the duration of the watchdog window by adjusting the external resistor (RROSC) value at the ROSC pin and setting the voltage level at the FSEL pin. The current through the RROSC resistor sets the clock frequency of the internal oscillator. The user can adjust the duration of the watchdog window (the watchdog timer period) by changing the resistor value. A high voltage level at the FSEL pin sets the watchdog window duration to 5 times as long as that of a low voltage level with same external component configuration.

The duration of the watchdog window and the duration of the fault output are multiples of the internal oscillator frequency, as shown by the following equations:

FSEL low
Equation 9. t(WD) = RROSC × 0.5 × 10-6
FSEL high
Equation 10. t(WD) = RROSC × 2.5 × 10-6
Watchdog initialization
Equation 11. t(WD_INI) = 8 × t(WD)

where:

  • t(WD) is the duration of the watchdog window
  • RROSC is the resistor connected at the ROSC pin
  • t(WD_INI) is the duration of the watchdog initialization

For all the foregoing items, the unit of resistance is Ω and the unit of time is s

Compared with window watchdog, there is no closed window in standard watchdog mode. The standard watchdog receives a service signal at any time within the watchdog window. The watchdog fault occurs when not servicing watchdog during the watchdog window.

Watchdog Service Signal and Watchdog Fault Outputs (WD and WDO)

The watchdog service signal (WD) must stay high for at least 100 µs. The WDO pin is the fault output terminal and is tied high through a pullup resistor to a regulated output supply. When a watchdog fault occurs, the devices momentarily pull WDO low for a duration of t(WD_HOLD).

Equation 12. TPS7B6333-Q1 TPS7B6350-Q1 eq12-tWDHOLD_SLVSD43.gif

ROSC Status Detection (ROSC)

When a watchdog function is enabled, if the ROSC pin is shorted to GND or open, the watchdog output (WDO) pin remains low, indicating a fault status. If the watchdog function is disabled, ROSC pin status detection does not work.

Watchdog Enable (PG and WD_EN)

When PG (power good) is high, an external microcontroller or a digital circuit can apply a high or low logic signal to the WD_EN pin to disable or enable the watchdog. A low input to this pin turns the watchdog on, and a high input turns the watchdog off. If PG is low, the watchdog is disabled and the watchdog-fault output (WDO) pin stays in the high-impedance state.

Watchdog Initialization

On power up and during normal operation, the watchdog initializes under the conditions shown in Table 2.

Table 2. Conditions for Watchdog Initialization

EDGE WHAT CAUSES THE WATCHDOG TO INITIALIZE
Rising edge of PG (power good) while the watchdog is in the enabled state, for example, during soft power up
Falling edge of WD_EN while PG is already high, for example, when the microprocessor enables the watchdog after the device is powered up
Rising edge of WDO while PG is already high and the watchdog is in the enabled state, for example, right after a closed window is serviced

Window Watchdog Operation (WTS = Low)

The window watchdog is able to monitor whether the frequency of the watchdog service signal (WD) is within certain ranges. A watchdog low-voltage fault is reported when the frequency of the watchdog service signal is out of the setting range. Figure 24 shows the window watchdog initialization and operation for the TPS7B63xx-Q1 (WRS is low). After the output voltage is in regulation and PG is high, the window watchdog becomes enabled when an external signal pulls WD_EN (the watchdog enable pin) low. This causes the watchdog to initialize and wait for a service signal during the first initialization window for 8 times the duration of t(WD). A service signal applied to the WD pin during the initialization open window resets the watchdog counter and a closed window starts. To prevent a fault condition from occurring, watchdog service must not occur during the closed window. Watchdog service must occur during the following open window to prevent a fault condition from occurring. The fault output (WDO), externally pulled up to VOUT (typical), stays high as long as the watchdog receives a proper service signal and there is no other fault condition.

TPS7B6333-Q1 TPS7B6350-Q1 wind-wd-oper_SLVSD43.gif Figure 24. Window Watchdog Operation

Three different fault conditions occur in Figure 24:

  • Fault 1: The watchdog service signal is received during the closed window. The WDO is triggered once, receiving a WD rising edge during the closed window.
  • Fault 2: The watchdog service signal is not received during the open window. WDO is triggered after the maximum open-window duration t(WD) / 2.
  • Fault 3: The watchdog service signal is not received during the WD initialization. WDO is triggered after the maximum initialization window duration 8 × t(WD).

Standard Watchdog Operation (WTS = High)

The standard watchdog is able to monitor whether the frequency of the watchdog service signal (WD) is lower than a certain value. A watchdog low-voltage fault is reported when the frequency of the watchdog service signal is lower than the set value.

Figure 25 shows the standard watchdog initialization and operation for the TPS7B63xx-Q1. Similar to the window watchdog, after output the voltage is in regulation and PG asserts high, the standard watchdog becomes enabled when an external signal pulls WD_EN low. This causes the standard watchdog to initialize and wait for a service signal during the first initialization window for 8 times the duration of t(WD). A service signal applied to the WD pin during the first open window resets the watchdog counter and another open window starts. To prevent a fault condition from occurring, watchdog service must occur during the every open window to prevent a fault condition from occurring. The fault output (WDO), externally pulled up to VOUT (typical), stays high as long as the watchdog receives proper service and there is not fault condition.

TPS7B6333-Q1 TPS7B6350-Q1 std-wd-oper_SLVSD43.gif Figure 25. Standard Watchdog Operation

Two different fault conditions occur in Figure 25:

  • Fault 1: The watchdog service signal is not received during the open window. WDO is triggered after the maximum open-window duration t(WD) / 2.
  • Fault 2: The watchdog service signal is not received during the WD initialization. WDO is triggered after the maximum initialization window duration 8 × t(WD).

Device Functional Modes

Operation With Input Voltage Lower Than 4 V

The devices normally operate with input voltages above 4 V. The devices can also operate at lower input voltages; the maximum UVLO voltage is 2.6 V. At input voltages below the actual UVLO voltage, the devices do not operate.

Operation With Input Voltage Higher Than 4 V

When the input voltage is greater than 4 V, if the input voltage is higher than the output set value plus the device dropout voltage, then the output voltage is equal to the set value. Otherwise, the output voltage is equal to the input voltage minus the dropout voltage.