The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically design to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.
The TPS7H3301-SP supports and is compliant to DDR, DDR2, DDR3, DDR4, and associated low-power JEDEC specifications. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT during suspend to RAM (S3) power down mode.
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(1)For all available packages, see the orderable addendum at the end of the data sheet.
(2) Applicable to DDR2, DDR3, DDR3L and DDR4. For DDR, input voltage = 3.3-V nominal. VIN is 2.95 to 3.5 V for DDR1 and VLDOIN > VTT for all DDRs. For DDR2 3-A load condition, VIN is 2.45 to 3.5 V. VIN headroom: VIN_MIN ≥ VTT + 1.5 V.
(3) These units are intended for engineering evaluation only. They are processed to a noncompliant flow (that is, no burn-in, and so forth) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life.
|DDR Memory Type|
|Iout VTT (Max) (A)|
|Iq (Typ) (mA)|
|Vin (Min) (V)|
|Vin (Max) (V)|
|Operating Temperature Range (C)|
|Package Size: mm2:W x L (PKG)|
|Vout VTT (Min) (V)|
Shutdown Pin for S3
-55 to 125
|See datasheet (CFP)|