SLOS732F June 2011  – May 2017 TRF7960A

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Application Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
  5. 5Specifications
    1. 5.1Absolute Maximum Ratings
    2. 5.2ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4Electrical Characteristics
    5. 5.5Thermal Resistance Characteristics
    6. 5.6Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Functional Block Diagram
    2. 6.2 Power Supplies
    3. 6.3 Supply Arrangements
    4. 6.4 Supply Regulator Settings
    5. 6.5 Power Modes
    6. 6.6 Receiver - Analog Section
      1. 6.6.1Main and Auxiliary Receiver
      2. 6.6.2Receiver Gain and Filter Stages
    7. 6.7 Receiver - Digital Section
      1. 6.7.1Received Signal Strength Indicator (RSSI)
        1. 6.7.1.1Internal RSSI - Main and Auxiliary Receivers
        2. 6.7.1.2External RSSI
    8. 6.8 Oscillator Section
    9. 6.9 Transmitter - Analog Section
    10. 6.10Transmitter - Digital Section
    11. 6.11Transmitter - External Power Amplifier or Subcarrier Detector
    12. 6.12Communication Interface
      1. 6.12.1General Introduction
      2. 6.12.2FIFO Operation
      3. 6.12.3Parallel Interface Mode
      4. 6.12.4Reception of Air Interface Data
      5. 6.12.5Data Transmission to MCU
      6. 6.12.6Serial Interface Communication (SPI)
        1. 6.12.6.1Serial Interface Mode Without Slave Select (SS)
        2. 6.12.6.2Serial Interface Mode With Slave Select (SS)
      7. 6.12.7Direct Mode
    13. 6.13Direct Commands from MCU to Reader
      1. 6.13.1 Command Codes
      2. 6.13.2 Reset FIFO (0x0F)
      3. 6.13.3 Transmission With CRC (0x11)
      4. 6.13.4 Transmission Without CRC (0x10)
      5. 6.13.5 Delayed Transmission With CRC (0x13)
      6. 6.13.6 Delayed Transmission Without CRC (0x12)
      7. 6.13.7 Transmit Next Time Slot (0x14)
      8. 6.13.8 Block Receiver (0x16)
      9. 6.13.9 Enable Receiver (0x17)
      10. 6.13.10Test Internal RF (RSSI at RX Input With TX On) (0x18)
      11. 6.13.11Test External RF (RSSI at RX Input With TX Off) (0x19)
      12. 6.13.12Register Preset
    14. 6.14Register Description
      1. 6.14.1Register Overview
        1. 6.14.1.1Main Configuration Registers
          1. 6.14.1.1.1Chip Status Control Register (0x00)
          2. 6.14.1.1.2ISO Control Register (0x01)
        2. 6.14.1.2Protocol Subsetting Registers
          1. 6.14.1.2.1 ISO14443B TX Options Register (0x02)
          2. 6.14.1.2.2 ISO14443A High-Bit-Rate and Parity Options Register (0x03)
          3. 6.14.1.2.3 TX Timer High Byte Control Register (0x04)
          4. 6.14.1.2.4 TX Timer Low Byte Control Register (0x05)
          5. 6.14.1.2.5 TX Pulse Length Control Register (0x06)
          6. 6.14.1.2.6 RX No Response Wait Time Register (0x07)
          7. 6.14.1.2.7 RX Wait Time Register (0x08)
          8. 6.14.1.2.8 Modulator and SYS_CLK Control Register (0x09)
          9. 6.14.1.2.9 RX Special Setting Register (0x0A)
          10. 6.14.1.2.10Regulator and I/O Control Register (0x0B)
        3. 6.14.1.3Status Registers
          1. 6.14.1.3.1IRQ Status Register (0x0C)
          2. 6.14.1.3.2Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
          3. 6.14.1.3.3RSSI Levels and Oscillator Status Register (0x0F)
        4. 6.14.1.4Test Registers
          1. 6.14.1.4.1Test Register (0x1A)
          2. 6.14.1.4.2Test Register (0x1B)
        5. 6.14.1.5FIFO Control Registers
          1. 6.14.1.5.1FIFO Status Register (0x1C)
          2. 6.14.1.5.2TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7960A Reader System Using SPI With SS Mode
      1. 7.1.1General Application Considerations
      2. 7.1.2Schematic
    2. 7.2System Design
      1. 7.2.1Layout Considerations
      2. 7.2.2Impedance Matching TX_Out (Pin 5) to 50 Ω
      3. 7.2.3Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1Getting Started and Next Steps
    2. 8.2Device Nomenclature
    3. 8.3Tools and Software
    4. 8.4Documentation Support
    5. 8.5Community Resources
    6. 8.6Trademarks
    7. 8.7Electrostatic Discharge Caution
    8. 8.8Export Control Notice
    9. 8.9Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Device Overview

Features

  • Completely Integrated Protocol Handling for ISO/IEC 15693, ISO/IEC 18000-3, ISO/IEC 14443A, ISO/IEC 14443B, NFC Forum Device Types 2 to 5, and FeliCa™
  • Input Voltage Range: 2.7 VDC to 5.5 VDC
  • Programmable Output Power:
    +20 dBm (100 mW) or +23 dBm (200 mW)
  • Programmable I/O Voltage Levels:
    1.8 VDC to 5.5 VDC
  • Programmable System Clock Frequency Output (RF, RF/2, RF/4)
  • Programmable Modulation Depth
  • Dual Receiver Architecture With RSSI for Elimination of "Read Holes" and Adjacent Reader System or Ambient In-Band Noise Detection
  • Programmable Power Modes for Ultra-Low-Power System Design (Power Down <0.5 µA)
  • Parallel or SPI Interface
  • Integrated Voltage Regulator for Microcontroller Supply
  • Temperature Range: –40°C to 110°C
  • 32-Pin QFN Package (5 mm × 5 mm) (RHB)

Applications

  • Secure Access Control
  • Product Authentication
  • Digital Door Locks
  • Public Transport or Event Ticketing
  • Medical Systems
  • Remote Sensor Applications

Description

The TRF7960A device is an integrated analog front-end (AFE) and multiprotocol data-framing device for a 13.56-MHz RFID reader/writer system that supports ISO/IEC 14443 A and B, Sony FeliCa, and ISO/IEC 15693. Built-in programming options make it suitable for a wide range of applications for proximity and vicinity identification systems.

The reader is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed.

The TRF7960A device supports data rates up to 848 kbps with all framing and synchronization tasks for the ISO protocols onboard. The device also supports reader/writer mode for NFC Forum tag types 1, 2, 3, 4, and 5. NFC Forum tag types 2, 3, 4, and 5 are supported with the built-in protocol decoders used in Direct Mode 2. NFC Forum tag type 1 requires the use of Direct Mode 0. Other standards and custom protocols can also be implemented by using Direct Mode 0. Direct Mode 0 lets the user fully control the AFE and also gain access to the raw subcarrier data or the unframed, but already ISO-formatted, data and the associated (extracted) clock signal.

The receiver system has a dual-input receiver architecture to maximize communication robustness. The receivers also include various automatic and manual gain control options. The received signal strength from transponders, ambient sources, or internal levels is available in the RSSI register.

A SPI or parallel interface can be used for the communication between the MCU and the TRF7960A reader. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 12-byte FIFO register. For direct transmit or receive functions, the encoders or decoders can be bypassed so the MCU can process the data in real time.

The TRF7960A device supports a wide supply voltage range of 2.7 V to 5.5 V and data communication levels from 1.8 V to 5.5 V for the MCU I/O interface.

The transmitter has selectable output power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply and supports OOK and ASK modulation with selectable modulation depth.

The built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and additional external circuits within the reader system.

Start evaluating the TRF7960A multiprotocol transceiver IC with the TRF7960AEVM or the TRF7960ATB.

Documentation, Tools, Reference Designs, and Software, Samples

Device Information(1)

PART NUMBERPACKAGEBODY SIZE
TRF7960ARHBVQFN (32)5 mm × 5 mm
For more information, see Section 9, Mechanical Packaging and Orderable Information.

Application Block Diagram

Figure 1-1 shows a typical application block diagram.

TRF7960A app_bd_slos732.gif Figure 1-1 Application Block Diagram