SCDS375A September   2017  – September 2017 TS5USBC402

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Powered-off Protection
      2. 8.3.2 Overvoltage Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Functions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFP|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VCC Supply voltage(3) –0.5 6 V
VI/O Input/Output DC voltage (D+, D-)(3) –0.5 20 V
VI/O Input/Output DC voltage (D1+/D1-, D2+/D2-) (3) –0.5 6 V
VI Digital input voltage (SEL1, SEL2, OE) –0.5 6 V
VO Digital output voltage (FLT) –0.5 6 V
IK Input-output port diode current (D+, D-, D1+, D1-, D2+, D2-) VIN < 0 –50 mA
IIK Digital logic input clamp current (SEL1, SEL2, OE) (3) VI < 0 –50 mA
ICC Continuous current through VCC 100 mA
IGND Continuous current through GND –100 mA
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 2.3 5.5 V
VI/O (D+, D-) Analog input/output voltage 0 18 V
VI/O (D1, D1-, D2+, D2-) 0 3.6 V
VI Digital input voltage (SEL1, SEL2, OE) 0 5.5 V
VO Digital output voltage (FLT) 0 5.5 V
II/O (D+, D-, D1+, D1-, D2+, D2-) Analog input/output port continuous current -50 50 mA
IOL Digital output current 3 mA
TA Operating free-air temperature (TS5USBC402) Standard 0 70 ºC
TA Operating free-air temperature (TS5USBC402I) Industrial –40 85 ºC
TJ Junction temperature –40 125 ºC

6.4 Thermal Information

THERMAL METRIC (1) TS5USBC402 UNIT
YFP
12 PINS
RθJA Junction-to-ambient thermal resistance 91.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.8 °C/W
RθJB Junction-to-board thermal resistance 22.8 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 23.0 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VCC Power supply voltage 2.3 5.5 V
ICC Active supply current OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or VCC
0 V < VI/O < 3.6 V		 72 100 µA
Supply current during OVP condition OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or VCC
VI/O > VPOS_THLD 		80 120 µA
ICC_PD Standby powered down supply current OE = 1.8 V or VCC
SEL1 = 0 V, 1.8 V, or VCC
SEL2 = 0 V, 1.8 V, or VCC		 2.2 10 µA
DC Characteristics
RON ON-state resistance VI/O = 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure 		5.6 9 Ω
ΔRON ON-state resistance match between channels VI/O = 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure 		0.07 0.3 Ω
RON (FLAT)  ON-state resistance flatness VI/O = 0 V to 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure 		0.07 0.4 Ω
IOFF I/O pin OFF leakage current VD± = 0 V or 3.6 V
VCC = 2.3 V to 5.5 V
VD1±or VD2+/- = 3.6 V or 0 V
Refer to Off Leakage Figure 		-1 1.2 6 µA
VD± = 0 V or  20 V
VCC = 2.3 V to 5.5 V
VD1± or VD2+/- = 0 V
Refer to Off Leakage Figure 		-1 165 200 µA
ION ON leakage current VD± = 0 V or 3.6 V
VD1± and VD2+/- = high-Z
Refer to On Leakage Figure 		-1 1.2 6 µA
Digital Characteristics
VIH Input logic high SEL1, SEL2, OE 1.4 V
VIL Input logic low SEL1, SEL2, OE 0.5 V
VOL Output logic low FLT
IOL = 3 mA		 0.4 V
IIH Input high leakage current SEL1, SEL2, OE = 1.8 V, VCC -1 1 5 μA
IIL Input low leakage current SEL1, SEL2, OE = 0 V -1 ±0.2 5 μA
RPD Internal pull-down resistor on digital input pins 6 MΩ
CI Digital input capacitance SEL1, SEL2 = 0 V, 1.8 V or VCC
f = 1 MHz		 3.4 pF
Protection
VOVP_TH OVP positive threshold 4.5 4.8 5.2 V
VOVP_HYST OVP threshold hysteresis 75 230 425 mV
VCLAMP_V Maximum voltage to appear on D1± and D2± pins during OVP scenario VD± = 0 to 18 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = Open
Switch on or off
OE = 0 V		 0 9.6 V
VD± = 0 to 18 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = 50Ω
Switch on or off
OE = 0 V		 0 9.0 V
tEN_OVP OVP enable time RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram Figure 		0.6 3 μs
tREC_OVP OVP recovery time RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram Figure 		1.5 5 μs

6.6 Dynamic Characteristics

TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COFF D+, D- off capacitance VD+/- = 0 or 3.3 V,
OE = VCC
f = 240 MHz		 Switch OFF 1.2 3.5 6.2 pF
D1+, D1-, D2+, D2- off capacitance VD+/- = 0 or 3.3 V,
OE = VCC or OE = 0V with SEL1, SEL2 (switch not selected)
f = 240 MHz		 Switch OFF or not selected 1.2 3.5 6.2 pF
CON IO pins ON capacitance VD+/- = 0 or 3.3 V,
f = 240 MHz		 Switch ON 1.4 4.5 6.2 pF
OISO Differential off isolation RL = 50 Ω
CL = 5 pF
f = 100 kHz
Refer to Off Isolation Figure 		Switch OFF -90 dB
RL = 50 Ω
CL = 5 pF
f = 240 MHz
Refer to Off Isolation Figure 		Switch OFF -22 dB
XTALK Channel to Channel crosstalk RL = 50 Ω
CL = 5 pF
f = 100 kHz
Refer to Crosstalk Figure 		Switch ON -90 dB
BW Bandwidth RL = 50 Ω; Refer to BW and Insertion Loss Figure Switch ON 1.2 GHz
ILOSS Insertion loss RL = 50 Ω
f = 240 MHz; Refer to BW and Insertion Loss Figure 		Switch ON -0.7 dB

6.7 Timing Requirements

TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tswitch Switching time between channels (SEL1, SEL2 to output) VD+/- = 0.8 V
Refer to Tswitch Timing Figure 		RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V		 0.45 1.2 µs
ton Device turn on time (OE to output) VD+/- = 0.8 V
Refer to Ton and Toff Figure 		100 250 µs
toff Device turn off time (OE to output) VD+/- = 0.8 V
Refer to Ton and Toff Figure 		0.35 1 µs
tSK(P) Skew of opposite transitions of same output (between D+ and D-) VD+/- = 0.4 V
Refer to Tsk Figure 		RL = 50 Ω,
CL = 1 pF,
VCC = 2.3 V to 5.5 V		 9 50 ps
tpd Propagation delay VD+/- = 0.4 V
Refer to Tpd Figure 		RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V		 130 180 ps

6.8 Typical Characteristics

TS5USBC402 D001_SCDS369.gif
VCC = 3.3 V TA = 25°C
Figure 1. ON-Resistance vs Input Voltage