TUSB1310A SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces | TI.com

TUSB1310A (NRND) SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces

SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces - TUSB1310A
Datasheet Errata

Special note

TI does not recommend using this part in a new design. This product continues to be in production to support existing customers.


The TUSB1310A device is one port, 5.0-Gbps USB 3.0 physical layer transceiver that operates off of one reference clock, which is provided by either a crystal or an external reference clock. The reference clock frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310A device provides the clock to the USB controller. The use of one reference clock allows the TUSB1310A device to provide a cost-effective USB 3.0 solution with few external components and a low implementation cost.

The USB controller interfaces to the TUSB1310A device through a PIPE (SuperSpeed) and a ULPI (USB 2.0) interface. The 16-bit PIPE operates off of a 250-MHz interface clock. The ULPI supports 8-bit operations with a 60-MHz interface clock.

USB 3.0 reduces active and idle power consumption with improved power-management features. The low-power states of the TUSB1310A device are controlled by the USB controller through the PIPE interface.

SuperSpeed USB uses existing USB software infrastructure by keeping the existing software interfaces and software drivers intact. In addition, SuperSpeed USB retains backward compatibility with USB 2.0 based products by using the same form-factor Type-A connector and cables. Existing USB 2.0 devices work with new USB 3.0 hosts and new USB 3.0 devices with work with legacy USB 2.0 hosts.


  • Universal Serial Bus (USB)
    • Single Port 5.0-Gbps USB 3.0 Physical Layer Transceiver
      • One 5.0-Gbps SuperSpeed Connection
      • One 480-Mbps HS/FS/LS Connection
    • Fully Compliant With USB 3.0 Specification, Revision 1.0
    • Supports 3+ Meters USB 3.0 Cable Length
    • Fully Adaptive Equalizer to Optimize Receiver Sensitivity
    • PIPE to Link-Layer Controller
      • Supports 16-Bit SDR Mode at 250 MHz
      • Compliant With PHY Interface for the USB Architectures (PIPE), Version 3.0
    • ULPI to Link-Layer Controller
      • Supports 8-Bit SDR Mode at 60 MHz
      • Supports Synchronous Mode and Low-Power Mode
      • Compliant With UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1
  • General Features
    • IEEE 1149.1 JTAG Support
    • IEEE 1149.6 JTAG support for the SuperSpeed Port
    • Operates on One Reference Clock of 40 MHz
    • 3.3-, 1.8-, and 1.1-V Supply Voltages
    • 1.8-V PIPE and ULPI I/O
    • Available in Lead-Free 175-Ball 12- × 12-nF NFBGA Package (ZAY)

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