SLLSE32G November   2010  – November 2017 TUSB1310A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
    2. 3.2 Configuration Pins
    3. 3.3 Signal Descriptions
      1. 3.3.1 PIPE
      2. 3.3.2 ULPI
      3. 3.3.3 Clocking
      4. 3.3.4 JTAG Interface
      5. 3.3.5 Reset and Output Control Interface
      6. 3.3.6 Strap Options
      7. 3.3.7 USB Interfaces
      8. 3.3.8 Special Connect
      9. 3.3.9 Power and Ground
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Device Power-Consumption Summary
    5. 4.5 DC Characteristics for 1.8-V Digital I/O
    6. 4.6 Thermal Characteristics
    7. 4.7 Timing Characteristics
      1. 4.7.1 Power-Up and Reset Timing
      2. 4.7.2 PIPE Transmit
      3. 4.7.3 PIPE Receive
      4. 4.7.4 ULPI Parameters
      5. 4.7.5 ULPI Clock
      6. 4.7.6 ULPI Transmit
      7. 4.7.7 ULPI Receive Timing
    8. 4.8 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Power On and Reset
        1. 5.3.1.1 RESETN and PHY_RESETN: Hardware Reset
        2. 5.3.1.2 ULPI Reset: Software Reset
        3. 5.3.1.3 OUT_ENABLE: Output Enable
        4. 5.3.1.4 Power-Up Sequence
      2. 5.3.2 Clocks
        1. 5.3.2.1 Clock Distribution
        2. 5.3.2.2 Output Clock
      3. 5.3.3 Power State Transition Time
      4. 5.3.4 Power Management
        1. 5.3.4.1 USB Power Management
      5. 5.3.5 Receiver Status
        1. 5.3.5.1 Clock Tolerance Compensation
        2. 5.3.5.2 Receiver Detection
        3. 5.3.5.3 8b/10b Decode Errors
        4. 5.3.5.4 Elastic Buffer Errors
        5. 5.3.5.5 Disparity Errors
      6. 5.3.6 Loopback
      7. 5.3.7 Adaptive Equalizer
    4. 5.4 Device Functional Modes
      1. 5.4.1 USB 3.0 Mode
      2. 5.4.2 USB 2.0 Mode
      3. 5.4.3 ULPI Modes
    5. 5.5 Register Maps
      1. 5.5.1  Vendor ID and Product ID (00h-03h)
      2. 5.5.2  Function Control (04h-06h)
      3. 5.5.3  Interface Control (07h-09h)
      4. 5.5.4  OTG Control
      5. 5.5.5  USB Interrupt Enable Rising (0Dh-0Fh)
      6. 5.5.6  USB Interrupt Enable Falling (10h-12h)
      7. 5.5.7  USB Interrupt Status (13h)
      8. 5.5.8  USB Interrupt Latch (14h)
      9. 5.5.9  Debug (15h)
      10. 5.5.10 Scratch Register (16-18h)
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 Clock Source Requirements
          1. 6.2.1.1.1 Clock Source Selection Guide
          2. 6.2.1.1.2 Oscillator
          3. 6.2.1.1.3 Crystal
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Chip Connection on PCB
          1. 6.2.2.1.1 USB Connector Pins Connection
          2. 6.2.2.1.2 Clock Connections
      3. 6.2.3 Application Curve
      4. 6.2.4 Layout
        1. 6.2.4.1 Layout Guidelines
          1. 6.2.4.1.1 High-Speed Differential Routing
          2. 6.2.4.1.2 SuperSpeed Differential Routing
        2. 6.2.4.2 Layout Example
    3. 6.3 Power Supply Recommendations
      1. 6.3.1 1.1-V and 1.8-V Digital Supply
      2. 6.3.2 1.1-V, 1.8-V and 3.3-V Analog Supplies
      3. 6.3.3 Capacitor Selection Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
      2. 7.1.2 Community Resources
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD1P1 steady-state supply voltage –0.3 1.4 V
VDD1P8 steady-state supply voltage –0.3 2.45 V
VDDA1P1 steady-state supply voltage –0.3 1.4 V
VDDA1P8 steady-state supply voltage –0.3 2.45 V
VDDA3P3 steady-state supply voltage –0.3 3.8 V
Storage temperature –55 150 °C

4.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDDA3P3 Analog 3.3-supply voltage 2.97 3.3 3.63 V
VDDA1P8 Analog 1.8-supply voltage 1.71 1.8 1.98 V
VDDA1P1 Analog 1.1-supply voltage 1.045 1.1 1.155 V
VDD1P8 Digital IO 1.8-supply voltage 1.62 1.8 1.98 V
VDD1P1 Digital 1.1-supply voltage 1.045 1.1 1.155 V
VBUS Voltage at VBUS PAD 0 1.155 V
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 105 °C

4.4 Device Power-Consumption Summary

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER MIN TYP MAX UNIT
VDDA3P3 power consumption 13 mW
VDDA1P8 power consumption 77 mW
VDDA1P1 power consumption 118 mW
VDD1P1 power consumption 98 mW
VDD1P8 power consumption 128 mW
(1) Power-consumption condition is transmitting and/or receiving (in U0) at 25°C and nominal voltages.

4.5 DC Characteristics for 1.8-V Digital I/O

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage 0.65 VDDS V
VIL Low-level input voltage 0.35 VDDS V
VOH High-level output voltage IO = –2 mA,
VDDS = 1.62 V to 1.98 V,
driver enabled, pullup or pulldown disabled		 VDDS – 0.45 V
IO = –2 mA,
VDDS = 1.4 V to 1.6 V,
driver enabled, pullup or pulldown disabled		 0.75 VDDS
VOL Low-level output voltage IO = 2 mA,
VDDS = 1.62 V to 1.98 V,
driver enabled, pullup or pulldown disabled		 0.45 V
IO = 2 mA,
VDDS = 1.4 V to 1.6 V,
driver enabled, pullup or pulldown disabled		 0.25 VDDS
Vhys Input hysteresis 100 270 mV
II Input current Any receiver, including those with a pullup or pulldown. The pullup or pulldown must be disabled. ±1 µA
II(PUon) Input current with pullup enabled Receiver pullup only, pullup enabled (not inhibited),
VPAD = 0 V		 –47 to –169 µA
Receiver pullup only, pullup enabled (not inhibited) –100
IOZ Off-state output current Driver only, driver disabled ±20 µA
IZ Total leakage current(1) ±20 µA
VTX_DIFF_SS SSTXP, SSTXN differential p-p TX voltage swing 0.8 1.2 V
RTX_DIFF_DC DC differential impedance 72 120 Ω
VTX_RCV_DET The amount of voltage change allowed during receiver detection 0.6 V
CAC_COUPLING AC coupling capacitor 75 200 nF
RRX_DC Receiver DC common-mode impedance 18 30 Ω
RRX_DIFF_DC DC differential impedance 72 120 Ω
VRX_LFPS_DET LFPS detect threshold 100 300 mV
VCM_AC_LFPS LFPS common-mode voltage 100 mV
VCM_LFPS_active LFPS common-mode voltage active 10 mV
VTX_DIFF_PP_LFPS LFPS differential voltage 800 1200 mV
(1) IZ is the total leakage current through the PAD connection of a driver/receiver combination that may include a pullup or pulldown. The driver output is disabled and the pullup or pulldown is inhibited.

4.6 Thermal Characteristics

THERMAL METRIC(1) TUSB1310A UNIT
ZAY (NFBGA)
175 PINS
RθJA Junction-to-ambient thermal resistance 34.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 21 °C/W
RθJB Junction-to-board thermal resistance 18.4 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 17.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

4.7 Timing Characteristics

4.7.1 Power-Up and Reset Timing

The TUSB1310A device does not drive signals on any strapping pins before they are latched internally.

TUSB1310A pwr_up_rst_tmng_llse32.gif Figure 4-1 Power-Up and Reset Timing

Table 4-1 Power-Up and Reset Timing

MIN NOM MAX UNIT
Tcfgin1 Hardware configuration latch-in time from RESETN 0 ns
Tcfgin2 Time from RESETN to driver outputs on strapping pins 0 ns
RESETN pulse width 1 µs
RESETN to PHY_STATUS deassertion 300 µs

4.7.2 PIPE Transmit

TUSB1310A pipe_transmt_llse32.gif Figure 4-2 PIPE Transmit Timing

Table 4-2 PIPE Transmit Timing

MIN NOM MAX UNIT
Tcyc2 TX_CLK period 4 ns
Tdty2 TX_CLK duty cycle 50%
Tsu2 Data setup to TX_CLK rise and TX_CLK fall(1) 1 ns
Thd2 Data hold to TX_CLK rise and TX_CLK fall(1) 0 ns
(1) This includes TX_DATA15-0, TX_DATAK1-0, TX_ONESZEROS, RATE, TX_DEEMPTH, TX_DETRX_LPBK, TX_ELECIDLE, TX_MARGIN, TX_SWING, RX_POLARITY, POWER_DOWN1-0.

4.7.3 PIPE Receive

TUSB1310A pipe_receive_llse32.gif Figure 4-3 PIPE Receive Timing

Table 4-3 PIPE Receive Timing

MIN NOM MAX UNIT
Tcyc3 PCLK Period 4 ns
Tdty3 PCLK Duty Cycle 50%
Tdly3 PCLK rise and fall to RX_DATA15-0, RX_DATAK1-0, RX_VALID, RX_STATUS2-0, PHY_STATUS Delay(1)(2) 1 2 ns
(1) Output Load max = 10 pF, min = 5 pF
(2) Timing is relative to the 50% transition point, not VIH or VIL.

4.7.4 ULPI Parameters

Table 4-4 ULPI Parameters

DESCRIPTION NOTES HS FS LS UNIT
RX CMD delay PHY pipeline delays 2 to 4 2 to 4 2 to 4 clocks
TX start delay 1 to 2 1 to 10 1 to 10 clocks
TX end delay 2 to 5 clocks
RX start delay 3 to 8 clocks
RX end delay 3 to 8 17 to 18 122 to 123 clocks
Transmit-Transmit (host only) Link decision times 15 to 24 7 to 18 77 to 247 clocks
Receive-Transmit (host or peripheral) 1 to 14 7 to 18 77 to 247 clocks

4.7.5 ULPI Clock

Table 4-5 ULPI Clock Parameters

MIN NOM MAX UNIT
Fstart_8bit Frequency (first transition) ±10% 54 60 66 MHz
Fsteady Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz
Dstart_8bit Duty cycle (first transition) ±10% 40% 50% 60%
Dsteady Duty cycle (steady state) ±500 ppm 49.975% 50% 50.025%
Tsteady Time to reach steady state frequency and duty cycle after first transition 1.4 ms
Tstart_dev Clock startup time after deassertion of SuspemdM – Peripheral 5.6 ms
Tstart_host Clock startup time after deassertion of SuspemdM – Hold ms
Tprep PHY preparation time after first transition of input clock µs
Tjitter Jitter ps
Trise, Tfall Rise and fall time ns

4.7.6 ULPI Transmit

TUSB1310A ulpi_transmt_tmg_llse32.gif Figure 4-4 ULPI Transmit Timing

Table 4-6 ULPI Transmit Timing

MIN NOM MAX UNIT
Tsc8, Tsd8 ULPI_STP set-up time 6 ns
Thc8, Thd8 ULPI_STP hold time 0 ns

4.7.7 ULPI Receive Timing

TUSB1310A ulpi_receive_tmg_llse32.gif Figure 4-5 ULPI Receive Timing

Table 4-7 ULPI Receive Timing

MIN NOM MAX UNIT
Tdc9, Tdd9 ULPI_DIR/ULPI_NXT/ULPI_DATA7-0(1) 9 ns
(1) Output Load MAX = 10 pF, MIN = 5 pF

4.8 Typical Characteristics

TUSB1310A C001_SLLSE32.png
Figure 4-6 TX De-emphasis
TUSB1310A C003_SLLSE32.png
Figure 4-8 Diff TX Swing versus Swing Settings
TUSB1310A C002_SLLSE32.png
Figure 4-7 TX Termination I-V