SLLSE76M March  2011  – July 2015 TUSB7320 , TUSB7340

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 3.3-V I/O Electrical Characteristics
    6. 6.6 Input Clock Specification
    7. 6.7 Input Clock 1.8-V DC Characteristics
    8. 6.8 Crystal Specification
    9. 6.9 TUSB7320 Power Consumption
    10. 6.10TUSB7340 Power Consumption
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1PHY Control
        1. 7.3.1.1Output Voltage Swing Control
          1. 7.3.1.1.1De-Emphasis Control
        2. 7.3.1.2Adaptive Equalizer
      2. 7.3.2Input Clock
        1. 7.3.2.1Clock Source Requirements
        2. 7.3.2.2External Clock
        3. 7.3.2.3External Crystal
    4. 7.4Programming
      1. 7.4.1Two-Wire Serial-Bus Interface
        1. 7.4.1.1Serial-Bus Interface Implementation
        2. 7.4.1.2Serial-Bus Interface Protocol
        3. 7.4.1.3Serial-Bus EEPROM Application
      2. 7.4.2System Management Interrupt
    5. 7.5Register Maps
      1. 7.5.1Classic PCI Configuration Space
        1. 7.5.1.1 The PCI Configuration Map
        2. 7.5.1.2 Vendor ID Register
        3. 7.5.1.3 Device ID Register
        4. 7.5.1.4 Command Register
        5. 7.5.1.5 Status Register
        6. 7.5.1.6 Class Code and Revision ID Register
        7. 7.5.1.7 Cache Line Size Register
        8. 7.5.1.8 Latency Timer Register
        9. 7.5.1.9 Header Type Register
        10. 7.5.1.10BIST Register
        11. 7.5.1.11Base Address Register 0
        12. 7.5.1.12Base Address Register 1
        13. 7.5.1.13Base Address Register 2
        14. 7.5.1.14Base Address Register 3
        15. 7.5.1.15Subsystem Vendor ID Register
        16. 7.5.1.16Subsystem ID Register
        17. 7.5.1.17Capabilities Pointer Register
        18. 7.5.1.18Interrupt Line Register
        19. 7.5.1.19Interrupt Pin Register
        20. 7.5.1.20Min Grant Register
        21. 7.5.1.21Max Latency Register
        22. 7.5.1.22Capability ID Register
        23. 7.5.1.23Next Item Pointer Register
        24. 7.5.1.24Power Management Capabilities Register
        25. 7.5.1.25Power Management Control/Status Register
        26. 7.5.1.26Power Management Bridge Support Extension Register
        27. 7.5.1.27Power Management Data Register
        28. 7.5.1.28MSI Capability ID Register
        29. 7.5.1.29Next Item Pointer Register
        30. 7.5.1.30MSI Message Control Register
        31. 7.5.1.31MSI Lower Message Address Register
        32. 7.5.1.32MSI Upper Message Address Register
        33. 7.5.1.33MSI Message Data Register
        34. 7.5.1.34Serial Bus Release Number Register (SBRN)
        35. 7.5.1.35Frame Length Adjustment Register (FLADJ)
        36. 7.5.1.36PCI Express Capability ID Register
        37. 7.5.1.37Next Item Pointer Register
        38. 7.5.1.38PCI Express Capabilities Register
        39. 7.5.1.39Device Capabilities Register
        40. 7.5.1.40Device Control Register
        41. 7.5.1.41Device Status Register
        42. 7.5.1.42Link Capabilities Register
        43. 7.5.1.43Link Control Register
        44. 7.5.1.44Link Status Register
        45. 7.5.1.45Device Capabilities 2 Register
        46. 7.5.1.46Device Control 2 Register
        47. 7.5.1.47Link Control 2 Register
        48. 7.5.1.48Link Status 2 Register
        49. 7.5.1.49Serial Bus Data Register
        50. 7.5.1.50Serial Bus Index Register
        51. 7.5.1.51Serial Bus Slave Address Regsiter
        52. 7.5.1.52Serial Bus Control and Status Register
        53. 7.5.1.53GPIO Control Register
        54. 7.5.1.54GPIO Data Register
        55. 7.5.1.55MSI-X Capability ID Register
        56. 7.5.1.56Next Item Pointer Register
        57. 7.5.1.57MSI-X Message Control Register
        58. 7.5.1.58MSI-X Table Offset and BIR Register
        59. 7.5.1.59MSI-X PBA Offset and BIR Register
        60. 7.5.1.60Subsystem Access Register
        61. 7.5.1.61General Control 0 Register
        62. 7.5.1.62General Control 1 Register
        63. 7.5.1.63General Control 2 Register
        64. 7.5.1.64USB Control Register
        65. 7.5.1.65De-Emphasis and Swing Control Register
        66. 7.5.1.66Equalizer Control Register
        67. 7.5.1.67Custom PHY Transmit/Receive Control Register
      2. 7.5.2PCI Express Extended Configuration Space
        1. 7.5.2.1 The PCI Express Extended Configuration Map
        2. 7.5.2.2 Advanced Error Reporting capability Register
        3. 7.5.2.3 Next Capability Offset / Capability Version Register
        4. 7.5.2.4 Uncorrectable Error Status Register
        5. 7.5.2.5 Uncorrectable Error Mask Register
        6. 7.5.2.6 Uncorrectable Error Severity Register
        7. 7.5.2.7 Correctable Error Severity Register
        8. 7.5.2.8 Correctable Error Mask Register
        9. 7.5.2.9 Advanced Error Capabilities and control Register
        10. 7.5.2.10Header Log Register
        11. 7.5.2.11Device Serial Number Capability ID Register
        12. 7.5.2.12Next Capability Offset/Capability Version Register
        13. 7.5.2.13Device Serial Number Register
      3. 7.5.3xHCI Memory Mapped Register Space
        1. 7.5.3.1The xHCI Register Map
        2. 7.5.3.2Host Controller Capability Registers
          1. 7.5.3.2.1Capability Registers Length
          2. 7.5.3.2.2Host Controller Interface Version Number
          3. 7.5.3.2.3Host Controller Structural Parameters 1
          4. 7.5.3.2.4Host Controller Structural Parameters 2
          5. 7.5.3.2.5Host Controller Structural Parameters 3
          6. 7.5.3.2.6Host Controller Capability Parameters
          7. 7.5.3.2.7Doorbell Offset
          8. 7.5.3.2.8Runtime Register Space Offset
        3. 7.5.3.3Host Controller Operational Registers
          1. 7.5.3.3.1 USB Command Register
          2. 7.5.3.3.2 USB Command Register
          3. 7.5.3.3.3 USB Status Register
          4. 7.5.3.3.4 Page Size Register
          5. 7.5.3.3.5 Device Notification Control Register
          6. 7.5.3.3.6 Command Ring Control Register
          7. 7.5.3.3.7 Device Context Base Address Array Pointer Register
          8. 7.5.3.3.8 Configure Register
          9. 7.5.3.3.9 Port Status and Control Register
          10. 7.5.3.3.10Port PM Status and Control Register (USB 3.0 Ports)
          11. 7.5.3.3.11Port PM Status and Control Register (USB 2.0 Ports)
          12. 7.5.3.3.12Port Link Info Register
        4. 7.5.3.4Host Controller Runtime Registers
          1. 7.5.3.4.1Microframe Index Register
          2. 7.5.3.4.2Interrupter Management Register
          3. 7.5.3.4.3Interrupter Moderation Register
          4. 7.5.3.4.4Event Ring Segment Table Size Register
          5. 7.5.3.4.5Event Ring Segment Table Base Address Register
          6. 7.5.3.4.6Event Ring Dequeue Pointer Register
        5. 7.5.3.5Host Controller Doorbell Registers
        6. 7.5.3.6xHCI Extended Capabilities Registers
          1. 7.5.3.6.1USB Legacy Support Capability Register
          2. 7.5.3.6.2USB Legacy Support Control/Status Register
          3. 7.5.3.6.3xHCI Supported Protocol Capability Register (USB 2.0)
          4. 7.5.3.6.4xHCI Supported Protocol Name String Register (USB 2.0)
          5. 7.5.3.6.5xHCI Supported Protocol Port Register (USB 2.0)
          6. 7.5.3.6.6xHCI Supported Protocol Capability Register (USB 3.0)
          7. 7.5.3.6.7xHCI Supported Protocol Name String Register (USB 3.0)
          8. 7.5.3.6.8xHCI Supported Protocol Port Register (USB 3.0)
      4. 7.5.4MSI-X Memory Mapped Register Space
        1. 7.5.4.1The MSI-X Table and PBA in Memory Mapped Register Space
      5. 7.5.5The MSI-X Table and PBA in Memory Mapped Register Space
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1Features
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
        1. 8.2.2.1Upstream Implementation
        2. 8.2.2.2Downstream Ports Implementation
        3. 8.2.2.3PCI Express Connector
        4. 8.2.2.41.1-V Regulator
        5. 8.2.2.55-V VBUS Options
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
    1. 9.1Power-Up and Power-Down Sequencing
      1. 9.1.1Power-Up Sequence
      2. 9.1.2Power-Down Sequence
    2. 9.2PCI Express Power Management
  10. 10Layout
    1. 10.1Layout Guidelines
      1. 10.1.1High-Speed Differential Routing
      2. 10.1.2SuperSpeed Differential Routing
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Device Nomenclature
    2. 11.2Documentation Support
      1. 11.2.1Related Documentation
        1. 11.2.1.1Related Documents
    3. 11.3Community Resources
    4. 11.4Related Links
    5. 11.5Trademarks
    6. 11.6Electrostatic Discharge Caution
    7. 11.7Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Features

  • USB 3.0-Compliant xHCI Host Controller
    • PCIe x1 Gen2 Interface
    • Four Downstream Ports
  • Two or Four Downstream Ports
  • Each Downstream Port
    • May Be Independently Enabled or Disabled
    • Has Adjustments for Transmit Swing, De-Emphasis, and Equalization Settings
    • May Be Marked as Removable or Nonremovable
    • Has Independent Power Control and Overcurrent Detection
  • Requires No External Flash for Default Configuration
    • Optional Serial EEPROM for Custom Configuration
  • Internal Spread Spectrum Generation
    • Low-Cost Crystal or Oscillator Support
  • Best-In-Class Adaptive Receiver Equalizer Design

Applications

  • Notebooks
  • Desktop Computers
  • Workstations
  • Servers
  • Add-In Cards and ExpressCard Implementations
  • PCI Express-Based Embedded Host Controllers for HDTVs, Set-Top Boxes and Gaming Console Applications

Description

The TUSB7320 supports up to two downstream ports. The TUSB7340 is a USB 3.0-compliant xHCI host controller that supports up to four downstream ports. Both parts are available in a pin-compatible 100-pin RKM package. For the remainder of this document, the name TUSB73x0 is used to reference both the TUSB7320 and the TUSB7340.

The TUSB73x0 interfaces to the host system through a PCIe x1 Gen 2 interface and provides SuperSpeed, high-speed, full-speed, or low-speed connections on the downstream USB ports.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
TUSB7320WQFN-MR (100)9.00 mm × 9.00 mm
TUSB7340
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application

TUSB7320 TUSB7340 typ_app_llse76.gif