SLLSEW5 April 2017 TUSB8044

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics, 3.3-V I/O
    6. 7.6Timing Requirements, Power-Up
    7. 7.7Hub Input Supply Current
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3I2C Programming Support Using Internal Hid to I2C Interface
        1. 8.3.3.1SET REPORT (Output)
        2. 8.3.3.2GET REPORT (Feature)
        3. 8.3.3.3GET REPORT (Input)
      4. 8.3.4USB2.0 Billboard
      5. 8.3.5One Time Programmable (OTP) Configuration
      6. 8.3.6Clock Generation
      7. 8.3.7Crystal Requirements
      8. 8.3.8Input Clock Requirements
      9. 8.3.9Power-Up and Reset
    4. 8.4Device Functional Modes
      1. 8.4.1External Configuration Interface
      2. 8.4.2I2C EEPROM Operation
      3. 8.4.3Port Configuration
      4. 8.4.4SMBus Slave Operation
    5. 8.5Register Maps
      1. 8.5.1 Configuration Registers
      2. 8.5.2 ROM Signature Register
      3. 8.5.3 Vendor ID LSB Register
      4. 8.5.4 Vendor ID MSB Register
      5. 8.5.5 Product ID LSB Register
      6. 8.5.6 Product ID MSB Register
      7. 8.5.7 Device Configuration Register
      8. 8.5.8 Battery Charging Support Register
      9. 8.5.9 Device Removable Configuration Register
      10. 8.5.10Port Used Configuration Register
      11. 8.5.11Device Configuration Register 2
      12. 8.5.12USB 2.0 Port Polarity Control Register
      13. 8.5.13UUID Registers
      14. 8.5.14Language ID LSB Register
      15. 8.5.15Language ID MSB Register
      16. 8.5.16Serial Number String Length Register
      17. 8.5.17Manufacturer String Length Register
      18. 8.5.18Product String Length Register
      19. 8.5.19Device Configuration Register 3
      20. 8.5.20USB 2.0 Only Port Register
      21. 8.5.21Billboard SVID LSB
      22. 8.5.22Billboard SVID MSB
      23. 8.5.23Billboard PID LSB
      24. 8.5.24Billboard PID MSB
      25. 8.5.25Billboard Configuration
      26. 8.5.26Billboard String1 Length
      27. 8.5.27Billboard String2 Length
      28. 8.5.28Serial Number String Registers
      29. 8.5.29Manufacturer String Registers
      30. 8.5.30Product String Registers
      31. 8.5.31Additional Feature Configuration Register
      32. 8.5.32SMBus Device Status and Command Register
      33. 8.5.33Billboard String1_2
  9. Applications and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Discrete USB Hub Product
        1. 9.2.1.1Design Requirements
        2. 9.2.1.2Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 PD Controller and EEPROM Implementation
          8. 9.2.1.2.8 DisplayPort Implementation
          9. 9.2.1.2.9 Clock, Reset, and Misc
          10. 9.2.1.2.10TUSB8044 Power Implementation
        3. 9.2.1.3Application Curves
  10. 10Power Supply Recommendations
    1. 10.1TUSB8044 Power Supply
    2. 10.2Downstream Port Power
    3. 10.3Ground
  11. 11Layout
    1. 11.1Layout Guidelines
      1. 11.1.1Placement
      2. 11.1.2Package Specific
      3. 11.1.3Differential Pairs
    2. 11.2Layout Examples
      1. 11.2.1Upstream Port
      2. 11.2.2Downstream Port
  12. 12Device and Documentation Support
    1. 12.1Receiving Notification of Documentation Updates
    2. 12.2Community Resources
    3. 12.3Trademarks
    4. 12.4Electrostatic Discharge Caution
    5. 12.5Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGC|64
Orderable Information

Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TUSB8044 is a four-port USB 3.1 Gen1 compliant hub. It provides simultaneous SuperSpeed USB and high-speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or low speed connections on the downstream port. The TUSB8044 can be used in any application that needs additional USB compliant ports. For example, a specific notebook may only have two downstream USB ports. By using the TUSB8044, the notebook can increase the downstream port count to five.

Typical Application

Discrete USB Hub Product

A common application for the TUSB8044 is as a self powered standalone USB Type-C docking product. The product is powered by an external 5V DC Power adapter. In this application, using a USB Type-C captive cable the TUSB8044 upstream port is plugged into a USB Host controller. The downstream ports of the TUSB8044 are exposed to users for connecting USB hard drives, cameras, flash drives, and so forth. There is also a DisplayPort receptacle for connected an external DisplayPort monitor.

TUSB8044 discrete_USB_hub_sllsew5.png Figure 35. Discrete USB Hub Product

Design Requirements

Table 41. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDD Supply1.1 V
VDD33 Supply3.3 V
Upstream Port USB Support (SS, HS, FS)SS, HS, FS
Downstream Port 1 USB Support (SS, HS, FS, LS)SS, HS, FS, LS
Downstream Port 2 USB Support (SS, HS, FS, LS)SS, HS, FS, LS
Downstream Port 3 USB Support (SS, HS, FS, LS)SS, HS, FS, LS
Downstream Port 4 USB Support (SS, HS, FS, LS)SS, HS, FS, LS
Number of Removable external exposed Downstream Ports4
Number of Non-Removable external exposed Downstream Ports0
Full Power Management of Downstream PortsYes. (FULLPWRMGMTZ = 0)
Individual Control of Downstream Port Power SwitchYes. (GANGED = 0)
Power Switch Enable PolarityActive High. (PWRCTL_POL = 1)
Battery Charge Support for Downstream Port 1Yes
Battery Charge Support for Downstream Port 2Yes
Battery Charge Support for Downstream Port 3Yes
Battery Charge Support for Downstream Port 4Yes
I2C EEPROM SupportYes
24MHz Clock SourceCrystal

Detailed Design Procedure

Upstream Port Implementation

The upstream of the TUSB8044 is connected to a USB Type-C captive cable. The system VBUS signal from the USB3 Type C plug is fed through a voltage divider. The purpose of the voltage divider is to make sure the system VBUS level meets TUSB8044 USB_VBUS input requirements. The voltage divider in this particular implementation will support up to 11.4V VBUS. If VBUS needs to be greater, then PD controller will need to directly control TUSB8044 USB_VBUS input. The USB-C plug has two pairs of USB3.1 differential pairs (RX1/TX1 and RX2/TX2). In this particular example, one pair of super speed signals (RX2 and TX2) from Type-C plug is connected to the DP Hub/Retimer/Redriver. The other pair of super speed signals (RX1 and TX2) is routed to the TUSB8044. The CC1 and VCONN signals from the Type-C plug is connected to the USB PD controller.

TUSB8044 sllsew5_type_c_up.gif Figure 36. Upstream Port Implementation

Downstream Port 1 Implementation

The downstream port 1 of the TUSB8044 is connected to a USB Type-C receptacle. With BATEN1 pin pulled up, Battery Charge support is enabled for Port 1. If Battery Charge support is not needed, then pull-up resistor on BATEN1 should be uninstalled. A 1:2 MUX passive MUX is used to route the hub downstream port's super speed signals to the appropriate location on the USB Type-C receptacle. The MUX orientation is controlled by the PD controller through the SEL signal. A example 1:2 passive MUX that could be used is the Texas Instrument's HD3SS3212.

TUSB8044 sllsew5_type_c_dp.gif Figure 37. Downstream Port 1 Implementation

Downstream Port 2 Implementation

The downstream port 2 of the TUSB8044 is connected to a USB3 Type A connector. With BATEN2 pin pulled up, Battery Charge support is enabled for Port 2. If Battery Charge support is not needed, then pull-up resistor on BATEN2 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI performance when the grounds are shorted together.

TUSB8044 sllsew5_downstream_port2.gif Figure 38. Downstream Port 2 Implementation

Downstream Port 3 Implementation

The downstream port3 of the TUSB8044 is connected to a USB3 Type A connector. With BATEN3 pin pulled up, Battery Charge support is enabled for Port 3. If Battery Charge support is not needed, then pull-up resistor on BATEN3 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI performance when the grounds are shorted together.

TUSB8044 sllsew5_downstream_port3.gif Figure 39. Downstream Port 3 Implementation

Downstream Port 4 Implementation

The downstream port 4 of the TUSB8044 is connected to a USB3 Type A connector. With BATEN4 pin pulled up, Battery Charge support is enabled for Port 4. If Battery Charge support is not needed, then pull-up resistor on BATEN4 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI performance when the grounds are shorted together.

TUSB8044 sllsew5_downstream_port4.gif Figure 40. Downstream Port 4 Implementation

VBUS Power Switch Implementation

This particular example uses the Texas Instruments TPS2561 Dual Channel Precision Adjustable Current-Limited power switch. For details on this power switch or other power switches available from Texas Instruments, refer to the Texas Instruments website.

TUSB8044 sllsew5_power_switch.gif Figure 41. VBUS Power Switch Implementation

PD Controller and EEPROM Implementation

In this specfic application, PD controller monitors and controls the CC line and the VBUS on both the upstream Type-C port and the downstream Type-C port. It also utilizes BBconfigure0 and BBconfigure1 to set up the billboard function of TUSB8044 and custom billboard information is stored in the EEPROM. Moreover, the controller uses the GPIOs to control the super speed MUX.

The TUSB8044 loads the 256 bytes plus the billboard strings from an external EEPROM. The billboard string starts at address 0x100 and ends at address 0x2DF for a total of 480 bytes. A minimum of 5.888Kbit EEPROM is recommended. EEPROMs do not come in this size so an 8Kbit EEPROM (10-bit addressing) is recommended. For example, an Atmel AT24C08A could be used.

TUSB8044 sllsew5_pd.gif Figure 42. PD Controller and EEPROM Implementation

DisplayPort Implementation

The DisplayPort interface can be implemented with a DisplayPort MST Hub or a DisplayPort redriver/retimer. The main channels and the AUX channels are connected to the DP receptacle after the HUB.

TUSB8044 sllsew5_display_port.gif Figure 43. DisplayPort Implementation

Clock, Reset, and Misc

The PWRCTL_POL is left unconnected which results in active high power enable (PWRCTL1, PWRCTL2, PWRCTL3, and PWRCTL4) for a USB VBUS power switch. SMBUSz pin is also left unconnected which will select I2C mode. Both PWRCTL_POL and SMBUSz pins have internal pull-ups. The 1 µF capacitor on the GRSTN pin can only be used if the VDD11 supply is stable before the VDD33 supply. The depending on the supply ramp of the two supplies the capacitor size may have to be adjusted.

TUSB8044 sllsew5_mics.gif Figure 44. Clock, Reset, and Misc

TUSB8044 Power Implementation

TUSB8044 sllsew5_power.gif Figure 45. TUSB8044 Power Implementation

Application Curves

TUSB8044 eye_us_sllsee4.gif
Figure 46. Upstream Port
TUSB8044 eye_ds2_sllsee4.gif
Figure 48. Downstream Port 2
TUSB8044 eye_ds4_sllsee4.gif
Figure 50. Downstream Port 4
TUSB8044 eye_hs_ds1_sllsee4.gif
Figure 52. High-Speed Downstream Port 1
TUSB8044 eye_hs_ds3_sllsee4.gif
Figure 54. High-Speed Downstream Port 3
TUSB8044 eye_ds1_sllsee4.gif
Figure 47. Downstream Port 1
TUSB8044 eye_ds3_sllsee4.gif
Figure 49. Downstream Port 3
TUSB8044 eye_hs_us_sllsee4.gif
Figure 51. High-Speed Upstream Port
TUSB8044 eye_hs_ds2_sllsee4.gif
Figure 53. High-Speed Downstream Port 2
TUSB8044 eye_hs_ds4_sllsee4.gif
Figure 55. High-Speed Downstream Port 4