SLLSEW5 April 2017 TUSB8044

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics, 3.3-V I/O
    6. 7.6Timing Requirements, Power-Up
    7. 7.7Hub Input Supply Current
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3I2C Programming Support Using Internal Hid to I2C Interface
        1. 8.3.3.1SET REPORT (Output)
        2. 8.3.3.2GET REPORT (Feature)
        3. 8.3.3.3GET REPORT (Input)
      4. 8.3.4USB2.0 Billboard
      5. 8.3.5One Time Programmable (OTP) Configuration
      6. 8.3.6Clock Generation
      7. 8.3.7Crystal Requirements
      8. 8.3.8Input Clock Requirements
      9. 8.3.9Power-Up and Reset
    4. 8.4Device Functional Modes
      1. 8.4.1External Configuration Interface
      2. 8.4.2I2C EEPROM Operation
      3. 8.4.3Port Configuration
      4. 8.4.4SMBus Slave Operation
    5. 8.5Register Maps
      1. 8.5.1 Configuration Registers
      2. 8.5.2 ROM Signature Register
      3. 8.5.3 Vendor ID LSB Register
      4. 8.5.4 Vendor ID MSB Register
      5. 8.5.5 Product ID LSB Register
      6. 8.5.6 Product ID MSB Register
      7. 8.5.7 Device Configuration Register
      8. 8.5.8 Battery Charging Support Register
      9. 8.5.9 Device Removable Configuration Register
      10. 8.5.10Port Used Configuration Register
      11. 8.5.11Device Configuration Register 2
      12. 8.5.12USB 2.0 Port Polarity Control Register
      13. 8.5.13UUID Registers
      14. 8.5.14Language ID LSB Register
      15. 8.5.15Language ID MSB Register
      16. 8.5.16Serial Number String Length Register
      17. 8.5.17Manufacturer String Length Register
      18. 8.5.18Product String Length Register
      19. 8.5.19Device Configuration Register 3
      20. 8.5.20USB 2.0 Only Port Register
      21. 8.5.21Billboard SVID LSB
      22. 8.5.22Billboard SVID MSB
      23. 8.5.23Billboard PID LSB
      24. 8.5.24Billboard PID MSB
      25. 8.5.25Billboard Configuration
      26. 8.5.26Billboard String1 Length
      27. 8.5.27Billboard String2 Length
      28. 8.5.28Serial Number String Registers
      29. 8.5.29Manufacturer String Registers
      30. 8.5.30Product String Registers
      31. 8.5.31Additional Feature Configuration Register
      32. 8.5.32SMBus Device Status and Command Register
      33. 8.5.33Billboard String1_2
  9. Applications and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Discrete USB Hub Product
        1. 9.2.1.1Design Requirements
        2. 9.2.1.2Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 PD Controller and EEPROM Implementation
          8. 9.2.1.2.8 DisplayPort Implementation
          9. 9.2.1.2.9 Clock, Reset, and Misc
          10. 9.2.1.2.10TUSB8044 Power Implementation
        3. 9.2.1.3Application Curves
  10. 10Power Supply Recommendations
    1. 10.1TUSB8044 Power Supply
    2. 10.2Downstream Port Power
    3. 10.3Ground
  11. 11Layout
    1. 11.1Layout Guidelines
      1. 11.1.1Placement
      2. 11.1.2Package Specific
      3. 11.1.3Differential Pairs
    2. 11.2Layout Examples
      1. 11.2.1Upstream Port
      2. 11.2.2Downstream Port
  12. 12Device and Documentation Support
    1. 12.1Receiving Notification of Documentation Updates
    2. 12.2Community Resources
    3. 12.3Trademarks
    4. 12.4Electrostatic Discharge Caution
    5. 12.5Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGC|64
Orderable Information

Detailed Description

Overview

The TUSB8044 is a four-port USB 3.1 Gen1 compliant hub. It provides simultaneous SuperSpeed USB and high-speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or low-speed connections on the downstream ports. When the upstream port is connected to an electrical environment that only supports high-speed or full-speed/low-speed connections, SuperSpeed USB connectivity is disabled on the downstream ports. When the upstream port is connected to an electrical environment that only supports full-speed/low-speed connections, SuperSpeed USB and high-speed connectivity are disabled on the downstream ports.

Functional Block Diagram

TUSB8044 fbd_8044_sllew5.gif

Feature Description

Battery Charging Features

The TUSB8044 provides support for USB Battery Charging (BC1.2) and custom charging. Battery charging support may be enabled on a per port basis through the REG_6h(batEn[3:0]).

USB Battery charging support includes both Charging Downstream Port (CDP) and Dedicated Charging Port (DCP) modes. The DCP mode is compliant with the Chinese Telecommunications Industry Standard YD/T 1591-2009. CDP is enabled when the upstream port has detected valid VBUS, configured, and host sets port power. When the upstream port is not connected and battery charging support is enabled, the TUSB8044 will enable DCP mode.

In addition to USB Battery charging (BC1.2), the TUSB8044 supports custom charging indications: Divider Charging (ACP3, ACP2, ACP1 modes), and Galaxy compatible charging. These custom charging modes are only supported when upstream port is unconnected and AUTOMODE is enabled. When in AUTOMODE and upstream port is disconnected, the port will automatically transition from ACP mode to the DCP mode depending on the portable device connected. The divided mode places a fixed DC voltage on the ports DP and DM signals which allows some devices to identify the capabilities of the charger. The default divider mode indicates support for up to 10W (ACP3). The divider mode can be configured to report a lower-current setting (up to 5 W) through REG_0Ah (HiCurAcpModeEn).

When the upstream port is not connected and battery charging support is enabled for a port, the TUSB8044 drives the port power enable active. If AUTOMODE is disabled, then DCP mode is used. If AUTOMODE is enabled and FullAutoEn bit is cleared (Reg_25h Bit 0), then TUSB8044 will start with highest enabled divider current mode (ACPx). The TUSB8044 will remain in highest current mode as long as a pull-up is not detected on DP pin. If an pull-up is detected on DP pin, then TUSB8044 will drive the port power enable inactive and switch to Galaxy mode, if enabled, or to DCP mode if Galaxy mode is disabled. The TUSB8044 will again drive the port power enable active. The TUSB8044 will remain in Galaxy mode as long as no pull-up is detected on DP pin. If an pull-up is detected on DP pin, then TUSB8044 will drive the port power enable inactive and transition to DCP mode. The TUSB8044 will again drive the port power enable active. In DCP mode, the TUSB8044 will look for a pull-up detected on DP pin or RxVdat. If a pull-up or RxVdat is detected on DP, the TUSB8044 will remain in DCP mode. If no pull-up or RxVdat is detected on DP pin after 2 seconds, the TUSB8044 will drive the port power enable inactive and transition back to ACPx mode. This sequence will repeat until upstream port is connected.

When Automatic mode is enabled and full automatic mode (FullAutoEn Reg_25h bit 0) is enabled, TUSB8044 will perform same sequence described in previous paragraph with the addition of attempting all supported ACPx modes before sequencing to Galaxy Mode (if enabled) or DCP mode.

The supported battery charging modes when TUSB8044 configured for SMBus or external EEPROM is detailed in Battery Charging Modes with SMBus/EEPROM Table.

The supported battery charging modes when TUSB8044 configured for I2C but without an external EEPROM is determined by the sampled state of the pins. These modes are detailed in Battery Charging Modes without EEPROM Table.

Table 1. TUSB8044 Battery Charging Modes with SMBus or I2C EEPROM

batEn[n] Reg_06h Bits 3:0Upstream VBUSHiCurAcpMode En Reg_0Ah Bit 4autoModeEnz Reg_0Ah Bit 1FullAutoEn Reg_25h Bit 0Galaxy_Enz Reg_25h Bit 1Battery Charging Mode Port x
(x = n + 1)
0Don’t CareDon't CareDon’t CareDon't CareDon't CareNo Charging support
1> 4VDon't CareDon't CareDon't CareDon't CareCDP
1< 4VDon't Care1Don't CareDon't CareDCP
1< 4V0011AUTOMODE enabled. Sequences through all ACPx modes and DCP with the exception of ACP3
Alternate ACP2, ACP1, DCP
1< 4V1011AUTOMODE enabled. Sequences through all ACPx modes and DCP.
Alternate ACP3, ACP2, ACP1, DCP
1< 4 V0001AUTOMODE enabled. Sequences between ACP2 and DCP.
Alternate ACP2, DCP
1< 4V1001AUTOMODE enabled. Sequences between ACP3 and DCP.
Alternate ACP3, DCP
1< 4V0010AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP2, ACP1, Galaxy, DCP.
1< 4V1010AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP3, ACP2, ACP1, Galaxy, DCP
1< 4V0000AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP2, Galaxy, DCP
1< 4V1000AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP3, Galaxy, DCP

Table 2. TUSB8044 Battery Charging Modes I2C Mode without EEPROM

BATEN[3:0] pinsUpstream VBUSGalaxy_Enz OTPBattery Charging Mode Port x
(x = n + 1)
0Don’t CareDon’t CareNo Charging support
1> 4VDon't CareCDP
1< 4V0AUTOMODE enabled with Galaxy compatible charging support. Sequences through all ACPx modes.
Alternate ACP3, ACP2, ACP1, Galaxy, DCP.
1< 4V1AUTOMODE enabled. Sequences through all ACPx modes.
Alternate ACP3, ACP2, ACP1, DCP.

USB Power Management

The TUSB8044 can be configured for power switched applications using either per-port (Full power managed) or ganged power-enable controls and over-current status inputs. When battery charge is enabled, the TUSB8044 will always function in full power managed.

Power switch support is enabled by REG_5h (fullPwrMgmtz) and the per-port or ganged mode is configured by REG_5h(ganged).

The TUSB8044 supports both active high and active low power-enable controls. The PWRCTL[4:1] polarity is configured by REG_Ah(pwrctlPol).

I2C Programming Support Using Internal Hid to I2C Interface

The TUSB8044 I2C programming mode is supported using class-specific requests through the HID interface. The HID's embedded port will be numbered 1 greater than the highest numbered exposed port. The internal HID to I2C function of the TUSB8044 does not have an interrupt OUT endpoint. The TUSB8044 supports GET REPORT (Input) through the HID interrupt and control endpoints. The GET REPORT (Feature) and SET REPORT (Output) occurs through the control endpoint.

Table 3. HID Requests I2C Programming Support

COMMAND bmRequestType bRequest wValue wIndex wLengthDATA
Setup field OffsetOffset = 0Offset = 1 Offset = 2 Offset = 4 Offset = 6N/A
GET REPORT A1H 01H 0100H – input
0300H - feature
0000H Report LengthReport
SET REPORT21H09H0200H – output0000HReport LengthReport

Other HID class specific requests are optional and not supported (SET IDLE, SET PROTOCOL, GET IDLE, GET PROTOCOL) . Also report IDs are not required since all requests are not interleaved.

SET REPORT (Output)

Report length includes overhead bytes (1 byte of opcode, 1 byte of device address and 2 bytes of data length) and must match the number of bytes sent in the data stage or the request will be stalled.

  • 1-byte opcode
    • 0x01 read I2C
    • 0x02 write I2C with stop
    • 0x03 write I2C without stop (use to set sub-address prior to read)
  • 1-byte I2C slave (7-bit) address
  • 2-byte I2C transaction data length
  • "length" bytes of Data for a write, but none for a read.

Set Report status stage reports only the status of the receipt and validity of the request, not the status of the I2C transaction. As long as the fields construct a valid request, the status stage will be Acked by a null packet. Otherwise, it will be STALLed. For example, if the report_length is longer than the amount of data sent before the status stage or the wLength is greater than the number of bytes of data sent in the data stage, the status stage will be STALLed. If the number of bytes sent in the data stage is greater than wLength or report_length, the data stage will be STALLED.

Software shall ensure properly formatted commands and data responses. The sum of the start address and wLength shall be less than the total size of the address range of the target device in a properly formatted command. Hardware shall wrap any data addresses above FFFFh and shall discard any data transmitted greater than wLength and return STALL. A STALL will also be returned if opcode is 00h.

The I2C master that performs the I2C reads and writes initiated through USB HID interface supports clock stretching. It operates at 400 kHz by default, but can be configured for 100 kHz through eFuse or register.

If the TUSB8044 is suspended (L2) by the USB host, the USB HID interface must enter suspend, but the I2C master shall remain active while attempting to complete an active I2C write request. An active I2C read request may be aborted if the TUSB8044 enters USB suspend state. Per the USB specification, the USB host should not suspend the HID interface while an I2C read or write is still in progress. The USB HID interface shall refuse requests to enter USB 2.0 sleep mode (L1) while an I2C read or write is in progress.

GET REPORT (Feature)

This HID Report will always return a 2-byte constant (0x82FF) which can be used to identify compatible HID devices even if the customer changes the VID/PID.

GET REPORT (Input)

A report length of one reports the status byte only. To receive a report with data, the report length must be the length of the data, plus one byte for status and two bytes for the length field.

  • 1-byte Status
    • 0 Success
    • 1 Fail — timeout (35 ms)
    • 2 Fail — Address nak
    • 3 Fail — data nak
  • 2-byte length
  • "length" bytes of Data for a read, but not for a write or a feature report.

A Get Report (input) request is required for both read and write. The interrupt endpoint will NAK until the I2C transaction is complete, so that it can report length, data for a read, and final status.

USB2.0 Billboard

Integrated in the TUSB8044 is a USB2.0 Billboard device which complies to the “USB Device Class Definition for Billboard Devices Version 1.1” specification. The billboard device is attached to the highest number downstream port of TUSB8044 USB2.0 hub. The purpose of the billboard is to communicate Alternate Mode status to the host system. The TUSB8044 supports only one Alternate Mode.

There are three pins, typically controlled by a USB Power Deliver (USB PD) controller, used to configure TUSB8044 Billboard functionality: BBEN, BBbmConfigured0, and BBbmConfigured1. The pins are only used when I2C mode is selected. If SMBus mode is selected, then TUSB8044 registers are used instead.

BBEN controls whether or not Billboard is presented to the Host system. When BBEN pin is high, the Billboard is presented to the Host system.

BBbmConfigured[1:0] pins map directly to the bmConfigured fields in the Billboard Capability Descriptor. These two pins must be set to reflect the Alternate Mode status before BBEN is asserted high. If Alternate Mode status changes after BBEN is high, BBEN must be transitioned low, BBbmConfigured[1:0] pins updated to reflect new status, and then BBEN asserted high. For cases in which USB PD controller only has one available GPIO to control TUSB8044 Billboard functionality, BBbmConfigured[1:0] pins should be tied to GND and BBEN pin must be asserted when an Alternate Mode failure occurs.

The TUSB8044 billboard capability descriptor fields can be changed using an external EEPROM. At power-up, the unique billboard fields from external EEPROM are loaded into TUSB8044 billboard. Fields controlled by EEPROM are described in Table 4. When an EEPROM is not used, the TUSB8044’s default values as indicated in Table 4 is used.

Table 4. EEPROM Billboard Capability Descriptor Map

SIZEI2C EEPROM ADDRESSTUSB8044 DEFAULT WHEN EEPROM NOT USEDDESCRIPTION
2-bytes0x28,0x270xFF01 (DisplayPort)SVID.
2-bytes0x2A,0x290x82EEBillboard PID. Billboard and hub will share the same VID.
1-byte0x2B0x80Billboard Configuration. When EEPROM used, this field must be set to 0x80.
1-byte0x2C0 = use default string in ROMBBString1Len. # of Unicode characters (2 bytes each) in string 1. BBString1Len size + BBString2Len size must be <= 480 bytes, or < 480 if # characters in string 1 is odd, because string 2 must start on an address that is a multiple of 4 (bytes).
1-byte0x2D0 = use default string in ROMBBString2Len. # of Unicode characters (2 bytes each) in string 2.
480 bytes0x100http://www.displayport.orgString 1. AdditionalInfoURL – required string descriptor providing a URL where the user can go to get more detailed information about the product and the various Alternate Modes it supports.
“DisplayPort”String 2. AlternateModeString – optional string to describe the alternate mode, which may include a URL. From Billboard spec, An example string is DisplayPort to VGA adapter. For further assistance, see http://help.vesa.org/dp-usb-type-c/.

One Time Programmable (OTP) Configuration

The TUSB8044 allows device configuration through one time programmable non-volatile memory (OTP). The programming of the OTP is supported using vendor-defined USB device requests. For details using the OTP features please contact your TI representative.

Table 5 provides a list features which may be configured using the OTP.

Table 5. OTP Configurable Features

CONFIGURATION REGISTER OFFSETBIT FIELDDESCRIPTION
REG_01h[7:0]Vendor ID LSB
REG_02h[7:0]Vendor ID MSB
REG_03h[7:0]Product ID LSB
REG_04h[7:0]Product ID MSB
REG_07h[0]Port removable configuration for downstream ports 1. OTP configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 = removable.
REG_07h[1]Port removable configuration for downstream ports 2. OTP configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 = removable.
REG_07h[2]Port removable configuration for downstream ports 3. OTP configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 = removable.
REG_07h[3]Port removable configuration for downstream ports 4. OTP configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 = removable.
REG_08h[3:0]Port used Configured register.
REG_0Ah[3]Enable Device Attach Detection..
REG_0Ah[4]High-current divider mode enable.
REG_0Bh[0]USB 2.0 port polarity configuration for downstream ports 1.
REG_0Bh[1]USB 2.0 port polarity configuration for downstream ports 2.
REG_0Bh[2]USB 2.0 port polarity configuration for downstream ports 3.
REG_0Bh[3]USB 2.0 port polarity configuration for downstream ports 4.
REG_25h[4:0]Device Configuration Register 3
REG_26h[3:0]USB2.0 Only Port Register
REG_F0h[3:1]USB power switch power-on delay.

Clock Generation

The TUSB8044 accepts a crystal input to drive an internal oscillator or an external clock source. If a clock is provided to XI instead of a crystal, XO is left open. Otherwise, if a crystal is used, the connection needs to follow the guidelines below. Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as possible and away from any switching leads. It is also recommended to minimize the capacitance between XI and XO. This can be accomplished by shielding C1 and C2 with the clean ground lines.

TUSB8044 clock_sllset2.gif Figure 2. TUSB8044 Clock

Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 pF - 24 pF and frequency stability rating of ±100 PPM or better. To ensure proper startup oscillation condition, a maximum crystal equivalent series resistance (ESR) of 50 Ω is recommended. A parallel load capacitor should be used if a crystal source is used. The exact load capacitance value used depends on the crystal vendor. Refer to application note Selection and Specification for Crystals for Texas Instruments USB2.0 devices (SLLA122) for details on how to determine the load capacitance value.

Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a ±100 PPM or better frequency stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak to peak jitter after applying the USB 3.1 jitter transfer function. XI should be tied to the 1.8-V clock source and XO should be left floating.

Power-Up and Reset

The TUSB8044 does not have specific power sequencing requirements with respect to the core power (VDD) or I/O and analog power (VDD33) as long as GRSTz is held in an asserted state while supplies ramp. The core power (VDD) or I/O power (VDD33) may be powered up for an indefinite period of time while the other is not powered up if all of these constraints are met:

  • All maximum ratings and recommended operating conditions are observed.
  • All warnings about exposure to maximum rated and recommended conditions are observed, particularly junction temperature. These apply to power transitions as well as normal operation.
  • Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the device.
  • Bus contention while VDD33 is powered down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when it is below that range, either stable or in transition.

A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in the recommended operating range to the de-assertion of GRSTz. This can be generated using programmable-delay supervisory device or using an RC circuit. When a RC circuit is used, the external capacitor size chosen must be large enough to meet the 3ms minimum duration requirement. The R of the RC circuit is the internal RPU.

Device Functional Modes

External Configuration Interface

The TUSB8044 supports a serial interface for configuration register access. The device may be configured by an attached I2C EEPROM or accessed as a slave by an external SMBus master. The external interface is enabled when both the SCL/SMBCLK and SDA/SMBDAT pins are pulled up to 3.3 V at the de-assertion of reset. The mode, I2C master or SMBus slave, is determined by the state of SMBUSz/SS_SUSPEND pin at reset. With the integrated USB HID to I2C master, the I2C interface can also be used to program an external EEPROM or perform updates of an external MCU's firmware.

I2C EEPROM Operation

The TUSB8044 supports a single-master, fast mode (400KHz) connection to a dedicated I2C EEPROM when the I2C interface mode is enabled. In I2C mode, the TUSB8044 reads the contents of the EEPROM at bus address 1010000b using 7-bit addressing starting at address 0. The TUSB8044 will read the entire EEPROM contents using a single burst read transaction. The burst read transaction will end when the address reaches 2DFh.

If the value of the EEPROM contents at address byte 00h equals 55h, the TUSB8044 loads the configuration registers according to the EEPROM map. If the first byte is not 55h, the TUSB8044 exits the I2C mode and continues execution with the default values in the configuration registers. The hub will not connect on the upstream port until the configuration is completed.

NOTE

The bytes located above offset Ah are optional. The requirement for data in those addresses is dependent on the options configured in the Device Configuration, and Device Configuration 2 registers.

The minimum size I2C EEPROM required is 8Kbit.

For details on I2C operation refer to the UM10204 I2C-bus Specification and User Manual.

Port Configuration

The TUSB8044 port configurations can be selected by registers or efuse. The Port Used Configuration register (USED[3:0]) define how many ports can possibly be reported by the hub. The device removable configuration register (RMBL[3:0]) define if the ports that are reported as used have permanently connected devices or not. The USB 2.0 Only Port register (USB2_ONLY[3:0]) define whether or a used port is reported as part of the USB 2.0 hub or both the USB2.0 and USB3.1 hubs. The USB2_ONLY field will enable the USB2.0 port even if the corresponding USED bit is low. The internal HID port will always be the second highest number USB2.0 port. The billboard port will always be the highest number USB2.0 port. The table below shows examples of the possible combinations.

Table 6. TUSB8044 Downstream Port Configuration Examples

USED[3:0]RMBL[3:0]USB2_ONLY
[3:0]
Reported Port ConfigurationPhysical to Logical Port mapping
1111111100004 Port USB3.1 Hub
6 Port USB2.0 Hub
Port 5 is permanently attached HID
Port 6 is permanently attached Billboard

Physical1 => Logical Port1 for USB3.1 and USB2.0.


Physical2 => Logical Port2 for USB3.1 and USB2.0.


Physical3 => Logical Port3 for USB3.1 and USB2.0.


Physical4 => Logical Port4 for USB3.1 and USB2.0.


Physical5 => Logical Port5 for USB2.0.


Physical6 => Logical Port6 for USB2.0.

1110111100003 Port USB3.1 Hub
5 Port USB2.0 Hub
Port 4 is permanently attached HID
Port 5 is permanently attached Billboard.

Physical1 Not used.


Physical2 => Logical Port1 for USB3.1 and USB2.0.


Physical3 => Logical Port2 for USB3.1 and USB2.0.


Physical4 => Logical Port3 for USB3.1 and USB2.0.


Physical5 => Logical Port4 for USB 2.0.


Physical6 => Logical Port5 for USB2.0.

1100011100002 Port USB 3.1 Hub
4 Port USB2.0 hub with permanently attached device on Port 2
Port 3 is a permanently attached HID
Port 4 is a permanently attached Billboard

Physical1 Not used.


Physical2 Not used.


Physical3 => Logical Port1 for USB3.1 and USB2.0.


Physical4 => Logical Port2 for USB3.1 and USB2.0.


Physical5 => Logical Port3 for USB2.0.


Physical6 => Logical Port4 for USB2.0.

0011111100101 Port USB 3.1 Hub
4 Port USB 2.0 Hub
Port 3 is a permanently attached HID
Port 4 is a permanently attached Billboard

Physical1 => Logical Port1 for USB3.1 and USB2.0.


Physical2 => Logical Port2 for USB2.0.


Physical3 Not Used.


Physical4 Not used.


Physical5 => Logical Port3 for USB2.0.


Physical6 => Logical Port4 for USB2.0.

1000111100101 Port USB 3.1 Hub
4 Port USB 2.0 Hub
Port 3 is a permanently attached HID
Port 4 is a permanently attached Billboard

Physical1 Not used.


Physical2 => Logical Port2 for USB2.0.


Physical3 Not used


Physical4 => Logical Port1 for USB3.1 and USB2.0.


Physical5 => Logical Port3 for USB2.0.


Physical6 => Logical Port4 for USB2.0.

1111111111101 Port USB 3.1 Hub
6 Port USB 2.0 Hub
Port 5 is a permanently attached HID
Port 6 is a permanently attached Billboard

Physical1 => Logical Port1 for USB3.1 and USB2.0.


Physical2 => Logical Port2 for USB2.0.


Physical3 => Logical Port3 for USB2.0.


Physical4 => Logical Port4 for USB2.0.


Physical5 => Logical Port5 for USB2.0.


Physical6 => Logical Port6 for USB2.0.

1010N/A0x0xInvalid combination when USB2_ONLY = 0000, 0001, 0100, or 0101. If invalid combination is used, then physical port 4 will not operate at USB3.1 Gen 1 speeds.
1011N/A0x01Invalid combination when USB2_ONLY = 0001 or 0101. If invalid combination is used, then physical port 4 will not operate at USB3.1 Gen 1 speeds.
1110N/A010xInvalid combination when USB2_ONLY = 0100 or 0101. If invalid combination is used, then physical port 4 will not operate at USB3.1 Gen 1 speeds.
1111N/A0101Invalid combination when USB2_ONLY = 0101. If invalid combination is used, then physical port 4 will not operate at USB3.1 Gen 1 speeds.

SMBus Slave Operation

When the SMBus interface mode is enabled, the TUSB8044 supports read block and write block protocols as a slave-only SMBus device.

If the TUSB8044 is addressed by a host using an unsupported protocol it will not respond. The TUSB8044 waits indefinitely for configuration by the SMBus host and will not connect on the upstream port until the SMBus host indicates configuration is complete by clearing the CFG_ACTIVE bit.

Table 7. TUSB8044 SMBus 7-bit address Mapping

TUSB8044 7-bit AddressRegister RangeDescription
7'b100010000h thru FFhBase 0 Registers
7'b1000101100h thru 1FFhBase 1 Registers for Billboard string 1 and 2
7'b1000110200h thru 2DFhBase 2 Registers for Billboard string 1 and 2

For details on SMBus requirements, refer to the System Management Bus Specification.

Register Maps

Configuration Registers

The internal configuration registers are accessed on byte boundaries. The configuration register values are loaded with defaults but can be over-written when the TUSB8044 is in I2C or SMBus mode.

Table 8. TUSB8044 Register Map

BYTE ADDRESSCONTENTSEEPROM CONFIGURABLE
00hROM Signature RegisterYes
01hVendor ID LSBYes
02hVendor ID MSBYes
03hProduct ID LSBYes
04hProduct ID MSBYes
05hDevice Configuration RegisterYes
06hBattery Charging Support RegisterYes
07hDevice Removable Configuration RegisterYes
08hPort Used Configuration RegisterYes
09hReserved. Must default to 00h. Yes
0AhDevice Configuration Register 2Yes
0BhUSB 2.0 Port Polarity Control RegisterYes
0Ch-0FhReservedNo
10h-1FhUUID Byte [15:0]No
20h-21hLangID Byte [1:0]Yes
22hSerial Number LengthYes
23hManufacturer String LengthYes
24hProduct String LengthYes
25hDevice Configuration Register 3Yes
26hUSB 2.0 Only Port RegisterYes
27hBillboard SVID LSBYes
28hBillboard SVID MSBYes
29hBillboard PID LSBYes
2AhBillboard PID MSBYes
2BhBillboard ConfigurationYes
2ChBillboard String1LenYes
2DhBillboard String2LenYes
2EhReservedNo
2FhReservedNo
30h-4FhSerial Number String Byte [31:0]Yes
50h-8FhManufacturer String Byte [63:0]Yes
90h-CFhProduct String Byte [63:0]Yes
D0h-D4hReservedYes(1)
D5h-D7hReservedNo
D8h-DChReservedYes(1)
DDh-EFhReservedNo
F0hAdditional Features Configuration RegisterYes
F1h-F7hReservedNo
F8hSMBus Device Status and Command RegisterNo
F9h - FFhReservedNo
100h - 2DFhUSB Billboard Strings 1 and 2Yes

ROM Signature Register

Figure 3. Register Offset 0h
Bit No.76543210
Reset State00000000

Table 9. Bit Descriptions – ROM Signature Register

BitFieldTypeDescription
7:0romSignatureRWROM Signature Register. This register is used by the TUSB8044 in I2C mode to validate the attached EEPROM has been programmed. The first byte of the EEPROM is compared to the mask 55h and if not a match, the TUSB8044 aborts the EEPROM load and executes with the register defaults.

Vendor ID LSB Register

Figure 4. Register Offset 1h
Bit No.76543210
Reset State01010001

Table 10. Bit Descriptions – Vendor ID LSB Register

BitFieldTypeDescription
7:0vendorIdLsbRO/RWVendor ID LSB. Least significant byte of the unique vendor ID assigned by the USB-IF; the default value of this register is 51h representing the LSB of the TI Vendor ID 0451h. The value may be over-written to indicate a customer Vendor ID.
Value used for this field will be the non-zero value written by EEPROM/SMBus to both PID and VID. If a zero value is written by EEPROM/SMbus to both PID and VID, then value used for this field will be the non-zero value from OTP. If a zero value is written by OTP, then value used for this field will be 51h.

Vendor ID MSB Register

Figure 5. Register Offset 2h
Bit No.76543210
Reset State00000100

Table 11. Bit Descriptions – Vendor ID MSB Register

BitFieldTypeDescription
7:0vendorIdMsbRO/RWVendor ID MSB. Most significant byte of the unique vendor ID assigned by the USB-IF; the default value of this register is 04h representing the MSB of the TI Vendor ID 0451h. The value may be over-written to indicate a customer Vendor ID.
Value used for this field will be the non-zero value written by EEPROM/SMBus to both PID and VID. If a zero value is written by EEPROM/SMbus to both PID and VID, then value used for this field will be the non-zero value from OTP. If a zero value is written by OTP, then value used for this field will be 04h.

Product ID LSB Register

Figure 6. Register Offset 3h
Bit No.76543210
Reset State01000000

Table 12. Bit Descriptions – Product ID LSB Register

BitFieldTypeDescription
7:0productIdLsbRO/RWProduct ID LSB. Least significant byte of the product ID assigned by Texas Instruments and reported in the SuperSpeed Device descriptor. the default value of this register is 40h representing the LSB of the SuperSpeed product ID assigned by Texas Instruments The value reported in the USB 2.0 Device descriptor is the value of this register bit wise XORed with 00000010b. The value may be over-written to indicate a customer product ID.
Value used for this field will be the non-zero value written by EEPROM/SMBus to both PID and VID. If a zero value is written by EEPROM/SMbus to both PID and VID, then value used for this field will be the non-zero value from OTP. If a zero value is written by OTP, then value used for this field will be 40h .

Product ID MSB Register

Figure 7. Register Offset 4h
Bit No.76543210
Reset State10000100

Table 13. Bit Descriptions – Product ID MSB Register

BitFieldTypeDescription
7:0productIdMsbRO/RWProduct ID MSB. Most significant byte of the product ID assigned by Texas Instruments; the default value of this register is 84h representing the MSB of the product ID assigned by Texas Instruments. The value may be over-written to indicate a customer product ID.
Value used for this field will be the non-zero value written by EEPROM/SMBus to both PID and VID. If a zero value is written by EEPROM/SMbus to both PID and VID, then value used for this field will be the non-zero value from OTP. If a zero value is written by OTP, then value used for this field will be 84h.

Device Configuration Register

Figure 8. Register Offset 5h
Bit No.76543210
Reset State00010000

Table 14. Bit Descriptions – Device Configuration Register

BitFieldTypeDescription
7customStringsRWCustom strings enable. This bit controls the ability to write to the Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers
0 = The Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers are read only
1 = The Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers may be loaded by EEPROM or written by SMBus
The default value of this bit is 0.
6customSernumRWCustom serial number enable. This bit controls the ability to write to the serial number registers.
0 = The Serial Number String Length and Serial Number String registers are read only
1 = Serial Number String Length and Serial Number String registers may be loaded by EEPROM or written by SMBus
The default value of this bit is 0.
5u1u2DisableRWU1 U2 Disable. This bit controls the U1/U2 support.
0 = U1/U2 support is enabled
1 = U1/U2 support is disabled, the TUSB8044 will not initiate or accept any U1 or U2 requests on any port, upstream or downstream, unless it receives or sends a Force_LinkPM_Accept LMP. After receiving or sending an FLPMA LMP, it will continue to enable U1 and U2 according to USB 3.1 protocol until it gets a power-on reset or is disconnected on its upstream port.
When the TUSB8044 is in I2C mode, the TUSB8044 loads this bit from the contents of the EEPROM.
When the TUSB8044 is in SMBUS mode, the value may be over-written by an SMBus host.
4RSVDROReserved. This bit is reserved and returns 1 when read.
3gangedRWGanged.
0 = When fullPwrMgmtz = 0, each port is individually power switched and enabled by the PWRCTL[4:1]/BATEN[4:1] pins
1 = When fullPwrMgmtz = 0, the power switch control for all ports is ganged and enabled by the PWRCTL[4:1]/BATEN1 pin
When the TUSB8044 is in I2C mode, the TUSB8044 loads this bit from the contents of the EEPROM.
When the TUSB8044 is in SMBUS mode, the value may be over-written by an SMBus host.
2fullPwrMgmtzRWFull Power Management.
0 = Port power switching status reporting is enabled
1 = Port power switching status reporting is disabled
When the TUSB8044 is in I2C mode, the TUSB8044 loads this bit from the contents of the EEPROM.
When the TUSB8044 is in SMBUS mode, the value may be over-written by an SMBus host.
1u1u2TimerOvrRWU1 U2 Timer Override. When this field is set, the TUSB8044 will override the downstream ports U1/U2 timeout values set by USB3.1 Host software. If software sets value in the range of 1h - FFh, the TUSB8044 will use the value of FFh. If software sets value to 0, then TUSB8044 will use value of 0.
0RSVDROReserved. This field is reserved and returns 0 when read.

Battery Charging Support Register

Figure 9. Register Offset 6h
Bit No.76543210
Reset State0000XXXX

Table 15. Bit Descriptions – Battery Charging Support Register

BitFieldTypeDescription
7:4RSVDROReserved. Read only, returns 0 when read.
3:0batEn[3:0]RWBattery Charger Support. The bits in this field indicate whether the downstream port implements the charging port features.
0 = The port is not enabled for battery charging support features
1 = The port is enabled for battery charging support features
Each bit corresponds directly to a downstream port, i.e. batEn0 corresponds to downstream port 1, and batEN1 corresponds to downstream port 2.
The default value for these bits are loaded at the de-assertion of reset with the value of PWRCTL/BATEN[3:0].
When in I2C/SMBus mode the bits in this field may be over-written by EEPROM contents or by an SMBus host.

Device Removable Configuration Register

Figure 10. Register Offset 7h
Bit No.76543210
Reset State0000XXXX

Table 16. Bit Descriptions – Device Removable Configuration Register

BitFieldTypeDescription
7customRmblRWCustom Removable. This bit controls the ability to write to the port removable bits, port used bits, and USB2_ONLY bits.
0 = rmbl[3:0], used[3:0], and USB2_ONLY[3:0] are read only and the values are loaded from the OTP ROM
1 = rmbl[3:0], used[3:0], and USB2_ONLY[3:0] are read/write and can be loaded by EEPROM or written by SMBus
This bit may be written simultaneously with rmbl[3:0].
6:4RSVDROReserved. Read only, returns 0 when read.
3:0rmbl[3:0]RO/RWRemovable. The bits in this field indicate whether a device attached to downstream ports 4 through 1 are removable or permanently attached.
0 = The device attached to the port is not removable
1 = The device attached to the port is removable
Each bit corresponds directly to a downstream port n + 1, i.e. rmbl0 corresponds to downstream port 1, rmbl1 corresponds to downstream port 2, etc.
This field is read only unless the customRmbl bit is set to 1. Otherwise the value of this filed reflects the inverted values of the OTP ROM non_rmb[3:0] field.

Port Used Configuration Register

Figure 11. Register Offset 8h
Bit No.76543210
Reset State00001111

Table 17. Bit Descriptions – Port Used Configuration Register

BitFieldTypeDescription
7:4RSVDROReserved. Read only.
3:0used[3:0]RO/RWUsed. The bits in this field indicate whether a port is enabled.
0 = The port is not used or disabled
1 = The port is used or enabled
Each bit corresponds directly to a downstream port, i.e. used0 corresponds to downstream port 1, used1 corresponds to downstream port 2, etc. All combinations are supported with the exception of both ports 1 and 3 marked as disabled. This field is read only unless the customRmbl bit is set to 1. When the corresponding USB2_ONLY bit is set, the USB2 port will be used and enabled regardless of the bit programmed into this field.

Device Configuration Register 2

Figure 12. Register Offset Ah
Bit No.76543210
Reset State00X10000

Table 18. Bit Descriptions – Device Configuration Register 2

BitFieldTypeDescription
7ReservedROReserved. Read-only, returns 0 when read.
6customBCfeaturesRWCustom Battery Charging Feature Enable. This bit controls the ability to write to the battery charging feature configuration controls.
0 = The HiCurAcpModeEn is read only and the values are loaded from the OTP ROM.
1 = The HiCurAcpModeEn bit is read/write and can be loaded by EEPROM or written by SMBus.
This bit may be written simultaneously with HiCurAcpModeEn.
5pwrctlPolRWPower enable polarity. This bit is loaded at the de-assertion of reset with the value of the PWRCTL_POL pin.
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
When the TUSB8044 is in I2C mode, the TUSB8044 loads this bit from the contents of the EEPROM.
When the TUSB8044 is in SMBUS mode, the value may be over-written by an SMBus host.
4HiCurAcpModeEnRO/RWHigh-current ACP mode enable. This bit enables the high-current tablet charging mode when the automatic battery charging mode is enabled for downstream ports.
0 = High current divider mode disabled . High current is ACP2 (default)
1 = High current divider mode enabled. High current mode is ACP3
This bit is read only unless the customBCfeatures bit is set to 1. If customBCfeatures is 0, the value of this bit reflects the value of the OTP ROM HiCurAcpModeEn bit.
3:2ReservedRWReserved
1autoModeEnzRWAutomatic Mode Enable.
The automatic mode only applies to downstream ports with battery charging enabled when the upstream port is not connected. Under these conditions:
0 = Automatic mode battery charging features are enabled.
1 = Automatic mode is disabled; only Battery Charging DCP and CDP mode is supported.
NOTE: When the upstream port is connected, Battery Charging CDP mode will be supported on all ports that are enabled for battery charging support regardless of the value of this bit.
0RSVDROReserved. Read only, returns 0 when read.

USB 2.0 Port Polarity Control Register

Figure 13. Register Offset Bh
Bit No.76543210
Reset State00000000

Table 19. Bit Descriptions – USB 2.0 Port Polarity Control Register

BitFieldTypeDescription
7customPolarityRWCustom USB 2.0 Polarity. This bit controls the ability to write the p[4:0]_usb2pol bits.
0 = The p[4:0]_usb2pol bits are read only and the values are loaded from the OTP ROM.
1 = The p[4:0]_usb2pol bits are read/write and can be loaded by EEPROM or written by SMBus.
This bit may be written simultaneously with the p[4:0]_usb2pol bits
6:5RSVDROReserved. Read only, returns 0 when read.
4p4_usb2polRO/RWDownstream Port 4 DM/DP Polarity. This controls the polarity of the port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0 the value of this bit reflects the value of the OTP ROM p4_usb2pol bit.
3p3_usb2polRO/RWDownstream Port 3 DM/DP Polarity. This controls the polarity of the port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0 the value of this bit reflects the value of the OTP ROM p3_usb2pol bit.
2p2_usb2polRO/RWDownstream Port 2 DM/DP Polarity. This controls the polarity of the port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0 the value of this bit reflects the value of the OTP ROM p2_usb2pol bit.
1p1_usb2polRORWDownstream Port 1 DM/DP Polarity. This controls the polarity of the port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0 the value of this bit reflects the value of the OTP ROM p1_usb2pol bit.
0p0_usb2polRO/RWUpstream Port DM/DP Polarity. This controls the polarity of the port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0 the value of this bit reflects the value of the OTP ROM p0_usb2pol bit.

UUID Registers

Figure 14. Register Offset 10h-1Fh
Bit No.76543210
Reset StateXXXXXXXX

Table 20. Bit Descriptions – UUID Byte N Register

BitFieldTypeDescription
7:0uuidByte[n]ROUUID byte N. The UUID returned in the Container ID descriptor. The value of this register is provided by the device and is meets the UUID requirements of Internet Engineering Task Force (IETF) RFC 4122 A UUID URN Namespace.

Language ID LSB Register

Figure 15. Register Offset 20h
Bit No.76543210
Reset State00001001

Table 21. Bit Descriptions – Language ID LSB Register

BitFieldTypeDescription
7:0langIdLsbRO/RWLanguage ID least significant byte. This register contains the value returned in the LSB of the LANGID code in string index 0. The TUSB8044 only supports one language ID. The default value of this register is 09h representing the LSB of the LangID 0409h indicating English United States.
When customStrings is 1, this field may be over-written by the contents of an attached EEPROM or by an SMBus host.

Language ID MSB Register

Figure 16. Register Offset 21h
Bit No.76543210
Reset State00000000

Table 22. Bit Descriptions – Language ID MSB Register

BitFieldTypeDescription
7:0langIdMsbRO/RWLanguage ID most significant byte. This register contains the value returned in the MSB of the LANGID code in string index 0. The TUSB8044 only supports one language ID. The default value of this register is 04h representing the MSB of the LangID 0409h indicating English United States.
When customStrings is 1, this field may be over-written by the contents of an attached EEPROM or by an SMBus host.

Serial Number String Length Register

Figure 17. Register Offset 22h
Bit No.76543210
Reset State00011000

Table 23. Bit Descriptions – Serial Number String Length Register

BitFieldTypeDescription
7:6RSVDROReserved. Read only, returns 0 when read.
5:0serNumStringLenRO/RWSerial number string length. The string length in bytes for the serial number string. The default value is 18h indicating that a 24 byte serial number string is supported. The maximum string length is 32 bytes.
When customSernum is 1, this field may be over-written by the contents of an attached EEPROM or by an SMBus host.
When the field is non-zero, a serial number string of serNumbStringLen bytes is returned at string index 1 from the data contained in the Serial Number String registers.

Manufacturer String Length Register

Figure 18. Register Offset 23h
Bit No.76543210
Reset State00000000

Table 24. Bit Descriptions – Manufacturer String Length Register

BitFieldTypeDescription
7RSVDROReserved. Read only, returns 0 when read.
6:0mfgStringLenRO/RWManufacturer string length. The string length in bytes for the manufacturer string. The default value is 0, indicating that a manufacturer string is not provided. The maximum string length is 64 bytes.
When customStrings is 1, this field may be over-written by the contents of an attached EEPROM or by an SMBus host.
When the field is non-zero, a manufacturer string of mfgStringLen bytes is returned at string index 3 from the data contained in the Manufacturer String registers.

Product String Length Register

Figure 19. Register Offset 24h
Bit No.76543210
Reset State00000000

Table 25. Bit Descriptions – Product String Length Register

BitFieldTypeDescription
7RSVDROReserved. Read only, returns 0 when read.
6:0prodStringLenRO/RWProduct string length. The string length in bytes for the product string. The default value is 0, indicating that a product string is not provided. The maximum string length is 64 bytes.
When customStrings is 1, this field may be over-written by the contents of an attached EEPROM or by an SMBus host.
When the field is non-zero, a product string of prodStringLen bytes is returned at string index 3 from the data contained in the Product String registers.

Device Configuration Register 3

Figure 20. Register Offset 25h
Bit No.76543210
Reset State00000000

Table 26. Bit Descriptions – Device Configuration Register 3

BitFieldTypeDescription
7:5RSVDROReserved. Read only, returns 0 when read.
4USB2.0_onlyRWUSB 2.0 hub reports as 2.0 only. This bit disables the USB 2.0 hub from reporting 5Gbps support in the wSpeedsSupported field of the USB SS BOS SS device capability descriptor. This bit will also disable the USB3.0 hub.
This bit is read/write but the read value returned is the Boolean OR of this bit and the corresponding eFuse bit. If either bit is set, this feature is enabled.
3ReservedROSwitch to reserved
2I2C_100kR/WI2C 100kHz. This bit controls the clock rate of the I2C master for both USB to I2C requests . The EEPROM reads will occur at 400K unless eFuse is used to set the rate to 100k.
This bit is read/write but the read value returned is the Boolean OR of this bit and the corresponding eFuse bit. If either bit is set, this feature is enabled.
1Galaxy_EnzR/WDisable Galaxy compatible modes. When this field is high, Galaxy charging compatible mode will not be included in AUTOMODE charger sequence.
This bit is read/write but the read value returned is the Boolean OR of this bit and the corresponding eFuse bit. If either bit is set, this feature is disabled.
0FullAutoEnR/WEnable all divider battery charging modes. When automode is enabled and this bit is set, any DS port enabled for battery charging will attempt all divider battery charging modes before DCP, starting with the highest current option.
The bit is writable, but the value read back is the Boolean OR of this bit and the corresponding eFuse control.
If either bit is set, eFuse or this register, this feature is enabled.

USB 2.0 Only Port Register

Figure 21. Register Offset 26h
Bit No.76543210
Reset State00000000

Table 27. Bit Descriptions – USB 2.0 Only Port Register

BitFieldTypeDescription
7:4RSVDROReserved. Read only, returns 0 when read.
3:0USB2_ONLY[3:0]RO/RWUSB 2.0 Only Ports. The bits in this field primarily indicate whether a port is enabled only for USB 2.0 operation. This field is read-only unless customRmbl bit is set. Also, these bits will override the corresponding USED bit.
A value of 0 indicates the hub port is enabled for both USB 3.1 and USB 2.0.
A value of 1 indicates the hub port is enabled only for USB 2.0 operation.

Billboard SVID LSB

Figure 22. Register Offset 27h (Billboard SVID LSB)
Bit No.76543210
Reset State00000001

Table 28. Bit Descriptions – Billboard SVID LSB

BitFieldTypeDescription
7:0SVID_LSBRWSVID. This field is the LSB of the 16-bit SVID. This field defaults to 0x01 but can be changed using an external I2C EEPROM or SMBus.

Billboard SVID MSB

Figure 23. Register Offset 28h (Billboard SVID MSB)
Bit No.76543210
Reset State11111111

Table 29. Bit Descriptions – Billboard SVID MSB

BitFieldTypeDescription
7:0SVID_MSBRWSVID. This field is the MSB of the 16-bit SVID. This field defaults to 0xFF but can be changed using an external I2C EEPROM or SMBus.

Billboard PID LSB

Figure 24. Register Offset 29h (Billboard PID LSB)
Bit No.76543210
Reset State11101110

Table 30. Bit Descriptions – Billboard PID LSB

BitFieldTypeDescription
7:0BBPID_LSBRWBillboard PID LSB. This field represents the LSB of the 16-bit PID. This field defaults to 0xEE but can be changed using an external I2C EEPROM or SMBus

Billboard PID MSB

Figure 25. Register Offset 2Ah (Billboard PID MSB)
Bit No.76543210
Reset State10000010

Table 31. Bit Descriptions – Billboard PID MSB

BitFieldTypeDescription
7:0BBPID_LSBRWBillboard PID MSB. This field represents the MSB of the 16-bit PID. This field defaults to 0x82 but can be changed using an external I2C EEPROM or SMBus.

Billboard Configuration

Figure 26. Register Offset 2Bh (Billboard Configuration)
Bit No.76543210
Reset State1000XX00

Table 32. Bit Descriptions – Billboard Configuration.

BitFieldTypeDescription
7:4VCONN_PWRRWVCONN power. This field is used when SMBus mode is selected. When I2C mode is selected, this field is read-only and will always return 1000b. The TUSB8044 will use value programmed into this register to update the VCONN Power field in the Billboard Capability Descriptor.
0000b: 1 Watt
0001b: 1.5 Watts
0010b: 2 Watts
0011b: 3 Watts
0100b: 4 Watts
0101b: 5 Watts
0110b: 6 Watts
0111b: Reserved.
1XXXb: The adapter does NOT require any Vconn power.
3:2bbConfigured[1:0]RWbmConfigured[1:0]. This field is used when SMBus mode is selected. Controls the bmConfigured[1:0] fields in the Billboard Capability Descriptor. When I2C mode is selected, then bmConfigured[1:0] fields are read-only and values are determined by BBbmConfigured[1:0] pins.
00b: Unspecified Error
01b: Alternate Mode Configuration Not attempted.
10b: Alternate Mode configured attempted but unsuccessful.
11b: Alternate Mode configured successfully.
1bAdditionalFailureInfoRWbAdditionalFailureInfo. This field is used when SMBus mode is selected. This field is ignored if VCONN_PWR[3] is set. The value programmed into this field will be presented in the bAdditionalFailureInfo field in the Billboard Capability Descriptor.
When in I2C mode, this field is read-only and defaults to 0.
0BillboardENRWBillboard Enable. This field is used when SMBus mode is selected. When I2C mode is selected, this field is read-only and Billboard connected state is determined by BBEN pin.
0b: Billboard not connected.
1b: Billboard connected.

Billboard String1 Length

Figure 27. Register Offset 2Ch (Billboard String1 Length)
Bit No.76543210
Reset State00101100

Table 33. Bit Descriptions – Billboard String1 Length.

BitFieldTypeDescription
7:0BBString1LenRWBillboard String1Len. This field indicates the length in number of UNICODE characters of the Billboard string1. This is not the length of the string descriptor. BBString1Len size + BBString2Len size must be <= 480 bytes, or < 480 if # characters in string 1 is odd, because string 2 must start on an address that is a multiple of 4 (bytes).

The bLength field of the Additional Info URL string descriptor is 2 + (2 * BBString1Len).


This field defaults to 0x2C but can be changed using an external I2C EEPROM or SMBus.

Billboard String2 Length

Figure 28. Register Offset 2Dh (Billboard String2 Length)
Bit No.76543210
Reset State00101100

Table 34. Bit Descriptions – Billboard String2 Length.

BitFieldTypeDescription
7:0BBString2LenRWBillboard String2Len. This field indicates the length in number of UNICODE characters of the Billboard string2. This is not the length of the string descriptor.

The bLength field of the Alternate Mode string descriptor is 2 + (2 * BBString2Len).


This field defaults to 0x2D but can be changed using an external I2C EEPROM or SMBus.

Serial Number String Registers

Figure 29. Register Offset 30h-4Fh
Bit No.76543210
Reset StateXXxxxxxx

Table 35. Bit Descriptions – Serial Number Registers

BitFieldTypeDescription
7:0serialNumber[n]RO/RWSerial Number byte N. The serial number returned in the Serial Number string descriptor at string index 1. The default value of these registers is assigned by TI. When customSernum is 1, these registers may be over-written by EEPROM contents or by an SMBus host.

Manufacturer String Registers

Figure 30. Register Offset 50h-8Fh
Bit No.76543210
Reset State00000000

Table 36. Bit Descriptions – Manufacturer String Registers

BitFieldTypeDescription
7:0mfgStringByte[n]RWManufacturer string byte N. These registers provide the string values returned for string index 3 when mfgStringLen is greater than 0. The number of bytes returned in the string is equal to mfgStringLen.
The programmed data should be in UNICODE UTF-16LE encodings as defined by The Unicode Standard, Worldwide Character Encoding, Version 5.0.

Product String Registers

Figure 31. Register Offset 90h-CFh
Bit No.76543210
Reset State00000000

Table 37. Bit Descriptions – Product String Byte N Register

BitFieldTypeDescription
7:0prodStringByte[n]RO/RWProduct string byte N. These registers provide the string values returned for string index 2 when prodStringLen is greater than 0. The number of bytes returned in the string is equal to prodStringLen.
The programmed data should be in UNICODE UTF-16LE encodings as defined by The Unicode Standard, Worldwide Character Encoding, Version 5.0.

Additional Feature Configuration Register

Figure 32. Register Offset F0h
Bit No.76543210
Reset State00000000

Table 38. Bit Descriptions – Additional Feature Configuration Register

BitFieldTypeDescription
7:5ReservedRWReserved. This field defaults to 3'b000 and must not be changed.
4stsOutputEn RWStatus output enable. This field when set enables of the Status output signals, HS_UP, HS_SUSPEND, SS_UP, SS_SUSPEND.
0 = STS outputs are disabled.
1 = STS outputs are enabled.
This bit may be loaded by EEPROM or over-written by a SMBUS host.
3:1pwronTimeRWPower On Delay Time. When the efuse_pwronTime field is all 0s, this field sets the delay time from the removal disable of PWRCTL to the enable of PWRCTL when transitioning battery charging modes. For example, when disabling the power on a transition from ACP to DCP Mode. The nominal timing is defined as follows:
Equation 1. TPWRON_EN = (pwronTime x 1) x 200 ms

This field may be over-written by EEPROM contents or by an SMBus host.
0usb3spreadDisRW USB3 Spread Spectrum Disable. This bit allows firmware to disable the spread spectrum function of the USB3 phy PLL.
0 = Spread spectrum function is enabled
1= Spread spectrum function is disabled
This bit may be loaded by EEPROM or over-written by a SMBUS host.

SMBus Device Status and Command Register

Figure 33. Register Offset F8h
Bit No.76543210
Reset State00000000

Table 39. Bit Descriptions – SMBus Device Status and Command Register

BitFieldTypeDescription
7:2RSVDROReserved. Read only, returns 0 when read.
1smbusRstRSUSMBus interface reset. This bit loads the registers back to their GRSTz values. Note, that since this bit can only be set when in SMBus mode the cfgActive bit is also reset to 1. When software sets this bit it must reconfigure the registers as necessary.
This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A write of 0 has no effect.
0cfgActiveRCUConfiguration active. This bit indicates that configuration of the TUSB8044 is currently active. The bit is set by hardware when the device enters the I2C or SMBus mode. The TUSB8044 shall not connect on the upstream port while this bit is 1.
When in I2C mode, the bit is cleared by hardware when the TUSB8044 exits the I2C mode.
When in the SMBus mode, this bit must be cleared by the SMBus host in order to exit the configuration mode and allow the upstream port to connect.
The bit is cleared by a writing 1. A write of 0 has no effect.

Billboard String1_2

Figure 34. Register Offset 100h - 2DFh (Billboard String1_2)
Bit No.76543210
Reset StateXXXXXXXX

Table 40. Bit Descriptions – Billboard String1_2

BitFieldTypeDescription
7:0BBString12WBillboard String1 and String2. This field can only be written to and can not be read from.
String 1 defaults http://www.displayport.org
String 2 defaults to "DisplayPort"
The default can be changed using an external I2C EEPROM or SMBus.