SLLSEW5 April 2017 TUSB8044

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics, 3.3-V I/O
    6. 7.6Timing Requirements, Power-Up
    7. 7.7Hub Input Supply Current
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3I2C Programming Support Using Internal Hid to I2C Interface
        1. 8.3.3.1SET REPORT (Output)
        2. 8.3.3.2GET REPORT (Feature)
        3. 8.3.3.3GET REPORT (Input)
      4. 8.3.4USB2.0 Billboard
      5. 8.3.5One Time Programmable (OTP) Configuration
      6. 8.3.6Clock Generation
      7. 8.3.7Crystal Requirements
      8. 8.3.8Input Clock Requirements
      9. 8.3.9Power-Up and Reset
    4. 8.4Device Functional Modes
      1. 8.4.1External Configuration Interface
      2. 8.4.2I2C EEPROM Operation
      3. 8.4.3Port Configuration
      4. 8.4.4SMBus Slave Operation
    5. 8.5Register Maps
      1. 8.5.1 Configuration Registers
      2. 8.5.2 ROM Signature Register
      3. 8.5.3 Vendor ID LSB Register
      4. 8.5.4 Vendor ID MSB Register
      5. 8.5.5 Product ID LSB Register
      6. 8.5.6 Product ID MSB Register
      7. 8.5.7 Device Configuration Register
      8. 8.5.8 Battery Charging Support Register
      9. 8.5.9 Device Removable Configuration Register
      10. 8.5.10Port Used Configuration Register
      11. 8.5.11Device Configuration Register 2
      12. 8.5.12USB 2.0 Port Polarity Control Register
      13. 8.5.13UUID Registers
      14. 8.5.14Language ID LSB Register
      15. 8.5.15Language ID MSB Register
      16. 8.5.16Serial Number String Length Register
      17. 8.5.17Manufacturer String Length Register
      18. 8.5.18Product String Length Register
      19. 8.5.19Device Configuration Register 3
      20. 8.5.20USB 2.0 Only Port Register
      21. 8.5.21Billboard SVID LSB
      22. 8.5.22Billboard SVID MSB
      23. 8.5.23Billboard PID LSB
      24. 8.5.24Billboard PID MSB
      25. 8.5.25Billboard Configuration
      26. 8.5.26Billboard String1 Length
      27. 8.5.27Billboard String2 Length
      28. 8.5.28Serial Number String Registers
      29. 8.5.29Manufacturer String Registers
      30. 8.5.30Product String Registers
      31. 8.5.31Additional Feature Configuration Register
      32. 8.5.32SMBus Device Status and Command Register
      33. 8.5.33Billboard String1_2
  9. Applications and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Discrete USB Hub Product
        1. 9.2.1.1Design Requirements
        2. 9.2.1.2Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 PD Controller and EEPROM Implementation
          8. 9.2.1.2.8 DisplayPort Implementation
          9. 9.2.1.2.9 Clock, Reset, and Misc
          10. 9.2.1.2.10TUSB8044 Power Implementation
        3. 9.2.1.3Application Curves
  10. 10Power Supply Recommendations
    1. 10.1TUSB8044 Power Supply
    2. 10.2Downstream Port Power
    3. 10.3Ground
  11. 11Layout
    1. 11.1Layout Guidelines
      1. 11.1.1Placement
      2. 11.1.2Package Specific
      3. 11.1.3Differential Pairs
    2. 11.2Layout Examples
      1. 11.2.1Upstream Port
      2. 11.2.2Downstream Port
  12. 12Device and Documentation Support
    1. 12.1Receiving Notification of Documentation Updates
    2. 12.2Community Resources
    3. 12.3Trademarks
    4. 12.4Electrostatic Discharge Caution
    5. 12.5Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Pin Configuration and Functions

RGC Package
64 Pin (VQFN)
(Top View)
TUSB8044 po_rgc_sllsew5.gif

Pin Functions

PINI/ODESCRIPTION
NAME NO.
Clock and Reset Signals
GRSTz 50 I
PU
Global power reset. This reset brings all of the TUSB8044 internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional.
XI 62 ICrystal input. This pin is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
XO 61 OCrystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
USB Upstream Signals
USB_SSTXP_UP 55 OUSB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_UP 56 OUSB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_UP 58 IUSB SuperSpeed receiver differential pair (positive)
USB_SSRXM_UP 59 IUSB SuperSpeed receiver differential pair (negative)
USB_DP_UP 53 I/OUSB High-speed differential transceiver (positive)
USB_DM_UP 54 I/OUSB High-speed differential transceiver (negative)
USB_R1 64 IPrecision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1 and GND.
USB_VBUS 48 IUSB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-KΩ ±1% resistor, and to ground through a 10-kΩ ±1% resistor from the signal to ground.
USB Downstream Signals
USB_SSTXP_DN1 3 OUSB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN1 4 OUSB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN1 6 IUSB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN1 7 IUSB SuperSpeed receiver differential pair (negative)
USB_DP_DN1 1 I/OUSB High-speed differential transceiver (positive)
USB_DM_DN1 2 I/OUSB High-speed differential transceiver (negative)
PWRCTL1/BATEN1 36 I/O, PDUSB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 1. This pin be left unconnected if power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 1 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR1z 46 I, PUUSB Port 1 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 1.
0 = An over current event has occurred
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
USB_SSTXP_DN2 11 OUSB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN2 12 OUSB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN2 14 IUSB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN2 15 IUSB SuperSpeed receiver differential pair (negative)
USB_DP_DN2 9 I/OUSB High-speed differential transceiver (positive)
USB_DM_DN2 10 I/OUSB High-speed differential transceiver (negative)
PWRCTL2/BATEN2 35 I/O, PDUSB Port 2 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 2. This pin be left unconnected if power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 2 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR2z 47 I, PUUSB Port 2 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 2.
0 = An over current event has occurred
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
USB_SSTXP_DN3 19 OUSB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN3 20 OUSB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN3 22 IUSB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN3 23 IUSB SuperSpeed receiver differential pair (negative)
USB_DP_DN3 17 I/OUSB High-speed differential transceiver (positive)
USB_DM_DN3 18 I/OUSB High-speed differential transceiver (negative)
PWRCTL3/BATEN3 33 I/O, PDUSB Port 3 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 3. This pin be left unconnected if power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 3 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR3z 44 I, PUUSB Port 3 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 3.
0 = An over current event has occurred
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
USB_SSTXP_DN4 26 OUSB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN4 27 OUSB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN4 29 IUSB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN4 30 IUSB SuperSpeed receiver differential pair (negative)
USB_DP_DN4 24 I/OUSB High-speed differential transceiver (positive)
USB_DM_DN4 25 I/OUSB High-speed differential transceiver (negative)
PWRCTL4/BATEN4 32 I/O, PDUSB Port 4 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 4. This pin be left unconnected if power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 4 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR4z 43 I, PUUSB Port 4 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 4.
0 = An over current event has occurred
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
I2C/SMBUS I2C Signals
SCL/SMBCLK 38 I/O, PDI2C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin acts as the serial clock interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host.
Can be left unconnected if external interface not implemented.
SDA/SMBDAT 37 I/O, PDI2C data/SMBus data. Function of pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin acts as the serial data interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host.
Can be left unconnected if external interface not implemented.
SMBUSz/SS_SUSPEND 39 I/O, PUI2C/SMBus mode select/SuperSpeed USB Suspend Status. The value of the pin is sampled at the de-assertion of reset set I2C or SMBus mode as follows:
1 = I2C Mode Selected
0 = SMBus Mode Selected
Can be left unconnected if external interface not implemented.
After reset, this signal indicates the SuperSpeed USB Suspend status of the upstream port if enabled through the stsOutputEn bit in the Additional Feature Configuration register. When enabled, a value of 1 indicates the connection is suspended.
Test and Miscellaneous Signals
PWRCTL_POL 41 I/O, PUPower Control Polarity.
The value of the pin is sampled at the de-assertion of reset to set the polarity of PWRCTL[4:1].
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
BBEN/GANGED/HS_UP42I/O, PDWhen configured for I2C mode, this pin functions as Billboard Enable. When high, the billboard device is enabled and presented to system. When low, the billboard device is disabled. If SMBus is selected, then Billboard enable is controlled by a register.

If SMBus is selected and stsOutputEn bit is set, this pin will function as a HS_UP (upstream HS connection indicator). When enabled, a value of 1 indicates the upstream port is connected to a High-speed USB capable port.


If SMBus is selected, the value of the pin is sampled at the de-assertion of reset to set the power switch and over current detection mode as follows: 0= Individual port power control supported. 1= Ganged port Power control supported. SMBus master can at a later time override the register.

BBbmConfigured0 /FULLAUTOz / FULLPWRMGMTz /SS_UP40I/O, PDWhen configured for I2C mode, this pin along with BBbmConfigured1 directly controls the bmConfigurated field in the Billboard Capability descriptor. If SMBus is selected, then bmConfigured[0] field is determined by a register.

If SMBus is selected and battery charginig is enabled on any port, the sampled state of this pin will set or clear the FullAutoEn bit in the Device Configuration Register 3. SMBus master can at a later time override the register.


If SMBus is selected and battery charging is disabled, then the value of the pin is sampled at the de-assertion of reset to set the power switch control: SMBus master can at a later time override this function.


0 = Power Switching and over current inputs supported.
1= Power Switch and over current inputs not supported.

If SMBus is selected and stsOutputEn bit is set, ths pin will function as a SS_UP (upstream SS connection indicator). When enabled, a value of 1 indicates the upstream port is connected to a SuperSpeed USB capable port.

BBbmConfigured1/AUTOENz/HS_SUSPEND45I/O, PDWhen configured for I2C mode, this pin along with BBbmConfigured0 directly controls the bmConfigurated field in the Billboard Capability descriptor. If SMBus is selected, then bmConfigured[1] field is determined by a register.

If SMBus is selected, the sampled value of this pin will set or clear the autoEnz bit in the Battery Charging Support Register. SMBus master can at a later time override the register.


If SMBus is selected and stsOutputEn bit is set, this pin will function as a HS_SUSPEND (upstream HS suspend indicator). When enabled, a value of 1 indicates the connection is suspended.

TEST 49 I, PDThis pin is reserved for factory test. It is suggested to have this pin pulled down to ground on PCB.
Power and Ground Signals
VDD 5, 8,
13, 21,
28, 31,
51, 57
PWR1.1-V power rail
VDD33 16, 34,
52, 63
PWR3.3-V power rail
VSS (Thermal Pad)PWRGround. Thermal pad must be connected to ground.
NC60No connect, leave floating