SLLSEW5 April 2017 TUSB8044


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics, 3.3-V I/O
    6. 7.6Timing Requirements, Power-Up
    7. 7.7Hub Input Supply Current
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3I2C Programming Support Using Internal Hid to I2C Interface
        1. REPORT (Output)
        2. REPORT (Feature)
        3. REPORT (Input)
      4. 8.3.4USB2.0 Billboard
      5. 8.3.5One Time Programmable (OTP) Configuration
      6. 8.3.6Clock Generation
      7. 8.3.7Crystal Requirements
      8. 8.3.8Input Clock Requirements
      9. 8.3.9Power-Up and Reset
    4. 8.4Device Functional Modes
      1. 8.4.1External Configuration Interface
      2. 8.4.2I2C EEPROM Operation
      3. 8.4.3Port Configuration
      4. 8.4.4SMBus Slave Operation
    5. 8.5Register Maps
      1. 8.5.1 Configuration Registers
      2. 8.5.2 ROM Signature Register
      3. 8.5.3 Vendor ID LSB Register
      4. 8.5.4 Vendor ID MSB Register
      5. 8.5.5 Product ID LSB Register
      6. 8.5.6 Product ID MSB Register
      7. 8.5.7 Device Configuration Register
      8. 8.5.8 Battery Charging Support Register
      9. 8.5.9 Device Removable Configuration Register
      10. 8.5.10Port Used Configuration Register
      11. 8.5.11Device Configuration Register 2
      12. 8.5.12USB 2.0 Port Polarity Control Register
      13. 8.5.13UUID Registers
      14. 8.5.14Language ID LSB Register
      15. 8.5.15Language ID MSB Register
      16. 8.5.16Serial Number String Length Register
      17. 8.5.17Manufacturer String Length Register
      18. 8.5.18Product String Length Register
      19. 8.5.19Device Configuration Register 3
      20. 8.5.20USB 2.0 Only Port Register
      21. 8.5.21Billboard SVID LSB
      22. 8.5.22Billboard SVID MSB
      23. 8.5.23Billboard PID LSB
      24. 8.5.24Billboard PID MSB
      25. 8.5.25Billboard Configuration
      26. 8.5.26Billboard String1 Length
      27. 8.5.27Billboard String2 Length
      28. 8.5.28Serial Number String Registers
      29. 8.5.29Manufacturer String Registers
      30. 8.5.30Product String Registers
      31. 8.5.31Additional Feature Configuration Register
      32. 8.5.32SMBus Device Status and Command Register
      33. 8.5.33Billboard String1_2
  9. Applications and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Discrete USB Hub Product
        1. Requirements
        2. Design Procedure
          1. Upstream Port Implementation
          2. Downstream Port 1 Implementation
          3. Downstream Port 2 Implementation
          4. Downstream Port 3 Implementation
          5. Downstream Port 4 Implementation
          6. VBUS Power Switch Implementation
          7. PD Controller and EEPROM Implementation
          8. DisplayPort Implementation
          9. Clock, Reset, and Misc
          10. Power Implementation
        3. Curves
  10. 10Power Supply Recommendations
    1. 10.1TUSB8044 Power Supply
    2. 10.2Downstream Port Power
    3. 10.3Ground
  11. 11Layout
    1. 11.1Layout Guidelines
      1. 11.1.1Placement
      2. 11.1.2Package Specific
      3. 11.1.3Differential Pairs
    2. 11.2Layout Examples
      1. 11.2.1Upstream Port
      2. 11.2.2Downstream Port
  12. 12Device and Documentation Support
    1. 12.1Receiving Notification of Documentation Updates
    2. 12.2Community Resources
    3. 12.3Trademarks
    4. 12.4Electrostatic Discharge Caution
    5. 12.5Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGC|64
Orderable Information


Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
Supply Voltage RangeVDD Steady-state supply voltage–0.31.4V
VDD33 Steady-state supply voltage–0.33.8V
Voltage RangeUSB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1], USB_SSRXN_DP[4:1] and USB_VBUS terminals-0.31.4V
XI terminals-0.32.45V
All other terminals-0.33.8V
Storage temperature, Tstg–65150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

V(ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±2000V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
VDD(1) 1.1V supply voltage0.991.11.26V
VDD33 3.3V supply voltage33.33.6V
USB_VBUSVoltage at USB_VBUS PAD01.155V
TA Operating free-air temperature TUSB8044070°C
TJ Operating junction temperature–40105°C
A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

Thermal Information

RθJA Junction-to-ambient thermal resistance 26°C/W
RθJCtop Junction-to-case (top) thermal resistance 11.5°C/W
RθJB Junction-to-board thermal resistance 5.3°C/W
ψJT Junction-to-top characterization parameter 0.2°C/W
ψJB Junction-to-board characterization parameter 5.2°C/W
RθJCbot Junction-to-case (bottom) thermal resistance 1.0°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics, 3.3-V I/O

over operating free-air temperature range (unless otherwise noted)
VIH High-level input voltage(1) VDD332VDD33V
VIL Low-level input voltage(1) VDD3300.8V
VI Input voltage0VDD33V
VO Output voltage(2) 0VDD33V
tt Input transition time (trise and tfall)025ns
Vhys Input hysteresis(3) 0.13 x VDD33V
VOH High-level output voltageVDD33IOH = -4 mA2.4V
VOL Low-level output voltageVDD33IOL = 4 mA0.4V
IOZ High-impedance, output current(2) VDD33VI = 0 to VDD33±20µA
IOZP High-impedance, output current with internal pullup or pulldown resistor(4) VDD33VI = 0 to VDD33±250µA
II Input current(5) VDD33VI = 0 to VDD33±15µA
RPDInternal pull-down resister13.51927.5K ohms
RPUInternal pull-up resistor14.51925K ohms
Applies to external inputs and bidirectional buffers.
Applies to external outputs and bidirectional buffers.
Applies to GRSTz.
Applies to pins with internal pullups/pulldowns.
Applies to external input buffers.

Timing Requirements, Power-Up

td1 VDD33 stable before VDD stable(3) See (2) ms
td2VDD and VDD33 stable before de-assertion of GRSTz3ms
tsu_ioSetup for MISC inputs(1) sampled at the de-assertion of GRSTz0.1µs
thd_ioHold for MISC inputs(1) sampled at the de-assertion of GRSTz0.1µs
tVDD33_RAMPVDD33 supply ramp requirements0.2100ms
tVDD_RAMP VDD supply ramp requirements 0.2 100 ms
MISC pins sampled at de-assertion of GRSTz: BATEN[4:1], SMBUSz, and PWRCTL_POL.
There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 µs before the VDD33.
An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz.
TUSB8044 pwr_up_timing_sllsee4.gif Figure 1. Power-Up Timing Requirements

Hub Input Supply Current

Typical values measured at TA = 25°C
3.3 V1.1 V
Power On (after Reset)                   330mA
Upstream Disconnect324mA
Suspend                                  330mA
ACTIVE MODES (US state / DS State)
3.0 host / 1 SS Device and Hub in U1 / U245240mA
3.0 host / 1 SS Device and Hub in U045356mA
3.0 host / 2 SS Devices and Hub in U1 / U245301mA
3.0 host / 2 SS Devices and Hub in U045457mA
3.0 host / 3 SS Devices and Hub in U1 / U245372mA
3.0 host / 3 SS Devices and Hub in U045563mA
3.0 host / 4 SS Devices and Hub in U1 / U245440mA
3.0 host / 4 SS Devices and Hub in U045672mA
3.0 host / 4 SS Devices and Hub in U0 plus Billboard enabled45680mA
3.0 host / 1 SS Device in U0 and 1 HS Device84372mA
3.0 host / 2 SS Devices in U0 and 2 HS Devices95512mA
2.0 host / HS Device4555mA
2.0 host / 4 HS Devices7674mA
2.0 host / 4 HS Devices plus Billboard enabled.7676mA