SLUSCV8 April 2017 UCC20225


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Power Ratings
    6. 6.6 Insulation Specifications
    7. 6.7 Safety-Related Certifications
    8. 6.8 Safety-Limiting Values
    9. 6.9 Electrical Characteristics
    10. 6.10Switching Characteristics
    11. 6.11Thermal Derating Curves
    12. 6.12Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1Propagation Delay and Pulse Width Distortion
    2. 7.2Rising and Falling Time
    3. 7.3PWM Input and Disable Response Time
    4. 7.4Programable Dead Time
    5. 7.5CMTI Testing
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2Input and Output Logic Table
      3. 8.3.3Input Stage
      4. 8.3.4Output Stage
      5. 8.3.5Diode Structure in UCC20225
    4. 8.4Device Functional Modes
      1. 8.4.1Disable Pin
      2. 8.4.2Programmable Dead Time (DT) Pin
        1. the DT Pin to VCC
        2. Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
  9. Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        1. PWM Input Filter
        2. External Bootstrap Diode and its Series Resistor
        3. Driver Output Resistor
        4. Gate Driver Power Loss
        5. Junction Temperature
        6. VCCI, VDDA/B Capacitor
          1. a VCCI Capacitor
          2. a VDDA (Bootstrap) Capacitor
          3. a VDDB Capacitor
        7. Time Setting Guidelines
        8. Circuits with Output Stage Negative Bias
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Certifications
    3. 12.3Receiving Notification of Documentation Updates
    4. 12.4Community Resources
    5. 12.5Trademarks
    6. 12.6Electrostatic Discharge Caution
    7. 12.7Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • NPL|13
Orderable Information


  • Single Input, Dual Output
  • 5-mm x 5-mm Space-Saving LGA-13 Package
  • Operating Temperature Range –40 to +125°C
  • Switching Parameters:
    • 19-ns Typical Propagation Delay
    • 10-ns Minimum Pulse Width
    • 5-ns Maximum Delay Matching
    • 6-ns Maximum Pulse-Width Distortion
  • Common-Mode Transient Immunity (CMTI) Greater than 100-V/ns
  • Surge Immunity up to 4600-V
  • 4-A Peak Source, 6-A Peak Sink Output
  • TTL and CMOS Compatible Inputs
  • 3-V to 18-V Input VCCI Range to Interface with Both Digital and Analog Controllers
  • Up to 25-V VDD Output Drive Supply
  • Programmable Dead Time
  • Rejects Input Pulses and Noise Transients Shorter than 5-ns
  • Fast Disable for Power Sequencing
  • Safety-Related and Regulatory Approvals:
    • 3535-VPK Isolation per DIN V VDE V 0884-10 and DIN EN 61010-1 (Planned)
    • 2500-VRMS Isolation for 1 Minute per UL 1577 (Planned)
    • CSA Component Acceptance Notice 5A, IEC 60950-1 IEC 61010-1 End Equipment Standards (Planned)
    • CQC Certification per GB4943.1-2011 (Planned)


  • Server, Telecom, IT and Industrial Infrastructures
  • Isolated Converters in Offline AC-to-DC Power Supplies
  • Motor Drive and DC-to-AC Solar Inverters
  • LED Lighting
  • HEV and BEV Battery Chargers


The UCC20225 is an isolated single input, dual-channel gate driver with 4-A source and 6-A sink peak current in a space-saving 5-mm x 5-mm LGA-13 package. It is designed to drive power MOSFETs, IGBTs, and SiC MOSFETs up to 5-MHz with best-in-class propagation delay and pulse-width distortion, in applications requiring the highest power density.

The input side is isolated from the two output drivers by a 2.5-kVRMS reinforced isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two secondary-side drivers allows a working voltage of up to 700-VDC.

This driver can be used for half-bridge driver with programmable dead time (DT). A disable pin shuts down both outputs simultaneously when it is set high, and allows normal operation when left open or grounded. As a fail-safe measure, primary-side logic failures force both outputs low.

The device accepts VDD supply voltages up to 25-V. A wide input VCCI range from 3-V to 18-V makes the driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under voltage lock-out (UVLO) protection.

With all these advanced features, the UCC20225 enables high power density, high efficiency, and robustness in a wide variety of power applications.

Device Information(1)

UCC20225NPLNPL LGA (13)5 mm × 5 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

UCC20225 fbd_sluscv8.gif

Revision History

April 2017*Initial Release.