SLUSCW3 August 2017 UCC27712-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6Dynamic Electrical Characteristics
    7. 7.7Typical Characteristics
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1VDD and Under Voltage Lockout
      2. 8.3.2Input and Output Logic Table
      3. 8.3.3Input Stage
      4. 8.3.4Output Stage
      5. 8.3.5Level Shift
      6. 8.3.6Low Propagation Delays and Tightly Matched Outputs
      7. 8.3.7Parasitic Diode Structure
    4. 8.4Device Functional Modes
      1. 8.4.1Minimum Input Pulse Operation
      2. 8.4.2Output Interlock and Dead Time
      3. 8.4.3Operation Under 100% Duty Cycle Condition
      4. 8.4.4Operation Under Negative HS Voltage Condition
  9. Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        1. 9.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 9.2.2.2Selecting Bootstrap Capacitor (CBOOT)
        3. 9.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
        4. 9.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 9.2.2.5Selecting Gate Resistor RON/ROFF
        6. 9.2.2.6Selecting Bootstrap Diode
        7. 9.2.2.7 Estimate the UCC27712-Q1 Power Losses (PUCC27712-Q1)
        8. 9.2.2.8Estimating Junction Temperature
        9. 9.2.2.9Operation With IGBT's
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Related Links
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Features

  • AEC-Q100 Qualified for Automotive Application
    • Device HBM Classification Level 1C
    • Device CDM Classification Level C4B
  • High-Side and Low-Side Configuration
  • Dual Inputs With Output Interlock and 150-ns Deadtime
  • Fully Operational up to 620-V, 700-V Absolute Maximum on HB Pin
  • 10-V to 20-V VDD Recommended Range
  • Peak Output Current 2.8-A Sink, 1.8-A Source
  • dv/dt Immunity of 50 V/ns
  • Logic Operational up to –11 V on HS Pin
  • Negative Voltage Tolerance On Inputs of –5 V
  • Large Negative Transient Safe Operating Area
  • UVLO Protection for Both Channels
  • Small Propagation Delay (100-ns Typical)
  • Delay Matching (12-ns Typical)
  • Low Quiescent Current
  • TTL and CMOS Compatible Inputs
  • Industry Standard SOIC-8 Package
  • All Parameters Specified Over Temperature Range, –40 °C to +125 °C

Applications

  • Automotive Inverters
  • On-Board Chargers (PFC, Phase-Shifted Full Bridge)
  • Motor Drive for Automotive Applications (Stepper Motors, Fans)

Description

The UCC27712-Q1 is a 620-V high-side and low-side gate driver with 1.8-A source, 2.8-A sink current, targeted to drive power MOSFETs or IGBTs.

The recommended VDD operating voltage is 10-V to 20-V for IGBT's and 10-V to 17-V for power MOSFETs.

The UCC27712-Q1 includes protection features where the outputs are held low when the inputs are left open or when the minimum input pulse width specification is not met. Interlock and deadtime functions prevent both outputs from being turned on simultaneously. In addition, the device accepts a wide range bias supply range from 10 V to 22 V, and offers UVLO protection for both the VDD and HB bias supply.

Developed with TI's state of the art high-voltage device technology, the device features robust drive with excellent noise and transient immunity including large negative voltage tolerance on its inputs, high dV/dt tolerance, wide negative transient safe operating area (NTSOA) on the switch node (HS), and interlock.

The device consists of one ground-referenced channel (LO) and one floating channel (HO) which is designed for operating with bootstrap or isolated power supplies. The device features fast propagation delays and excellent delay matching between both channels. On the UCC27712-Q1, each channel is controlled by its respective input pins, HI and LI.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
UCC27712-Q1SOIC (8)3.91 mm × 8.65 mm
For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

UCC27712-Q1 alt_sluscw3.gif

Typical Propagation Delay Comparison

UCC27712-Q1 TypicalCompare_slusce9.gif