ADC08DJ3200 8-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC) | TI.com

ADC08DJ3200 (ACTIVE)

8-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC)

 

Description

The ADC08DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC08DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. At 5 GSPS, only four total lanes are required running at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications.

Features

  • ADC Core:
    • 8-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Performance Specifications (fIN = 997 MHz):
    • ENOB: 7.8 Bits
    • SFDR:
      • Dual-Channel Mode: 67 dBFS
      • Single-Channel Mode: 62 dBFS
  • Buffered Analog Inputs With VCMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: >10 GHz
    • Full-Scale Input Voltage (VFS, Default): 0.8 VPP
    • Analog Input Common-Mode (VICM): 0 V
  • Noiseless Aperture Delay (TAD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • JESD204B Serial Data Interface:
    • Supports Subclass 0 and 1
    • Maximum Lane Rate: 12.8 Gbps
    • Up to 16 Lanes Allows Reduced Lane Rate
  • Power Consumption: 2.8 W
  • Power Supplies: 1.1 V, 1.9 V

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Parametrics Compare all products in High-speed ADCs (>10MSPS)

 
Sample Rate (Max) (MSPS)
Features
Resolution (Bits)
Number of input channels
SNR (dB)
ENOB (Bits)
SFDR (dB)
Power consumption (Typ) (mW)
Input range (Vp-p)
Interface
Operating temperature range (C)
Analog input BW (MHz)
Input buffer
Package Group
Package size: mm2:W x L (PKG)
Rating
Architecture
DNL (Typ) (+/-LSB)
INL (Typ) (+/-LSB)
Reference mode
ADC08DJ3200 ADC12DJ2700 ADC12DJ3200 ADC12DL3200
3200
6400    
2700
5400    
3200
6400    
3200
6400    
Ultra High Speed     Ultra High Speed     Ultra High Speed     Ultra High Speed    
8     12     12     12    
2
1    
2
1    
2
1    
2
1    
49.1     56.7     56.6     57.1    
7.8     9     9     9    
67
62    
71     67     70    
2800     2700     3000     3150    
0.8     0.8     0.8     0.8    
JESD204B     JESD204B     JESD204B     DDR LVDS
Parallel LVDS    
-40 to 85     -40 to 85     -40 to 85     -40 to 85    
8000     8000     8000     8000    
Yes     Yes     Yes     Yes    
FCBGA | 144     FCBGA | 144     FCBGA | 144     FCBGA | 256    
See datasheet (FCBGA)     See datasheet (FCBGA)     See datasheet (FCBGA)     See datasheet (FCBGA)    
Catalog     Catalog     Catalog     Catalog    
Folding Interpolating     Folding Interpolating     Folding Interpolating     Folding Interpolating    
0.15     0.7
-0.3    
0.3     0.3    
0.3     2     2.5     2    
Int     Int     Int     Int