SLVSD97 June 2017 ADC12DJ3200

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - DC Specifications
    6. 6.6 Electrical Characteristics - Power Consumption
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Switching Characteristics
    10. 6.10Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagrams
    3. 7.3Feature Description
      1. 7.3.1Analog Inputs
        1. 7.3.1.1Analog Input Protection
        2. 7.3.1.2Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3Analog Input Offset Adjust
      2. 7.3.2ADC Core
        1. 7.3.2.1ADC Theory of Operation
        2. 7.3.2.2ADC Core Calibration
        3. 7.3.2.3ADC Over-Range Detection
        4. 7.3.2.4Code Error Rate (CER)
      3. 7.3.3Timestamp
      4. 7.3.4Clocking
        1. 7.3.4.1Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2Automatic SYSREF Calibration
      5. 7.3.5Digital Down Converters (Dual Channel Mode Only)
        1. 7.3.5.1Numerically Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2NCO Selection
          3. 7.3.5.1.3Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5NCO Phase Offset Setting
          6. 7.3.5.1.6NCO Phase Synchronization
        2. 7.3.5.2Decimation Filters
        3. 7.3.5.3Output Data Format
        4. 7.3.5.4Decimation Settings
          1. 7.3.5.4.1Decimation Factor
          2. 7.3.5.4.2DDC Gain Boost
      6. 7.3.6JESD204B Interface
        1. 7.3.6.1Transport Layer
        2. 7.3.6.2Scrambler
        3. 7.3.6.3Link Layer
          1. 7.3.6.3.1Code Group Synchronization (CGS)
          2. 7.3.6.3.2Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.38b/10b Encoding
          4. 7.3.6.3.4Frame and Multiframe Monitoring
        4. 7.3.6.4Physical Layer
          1. 7.3.6.4.1Serdes Pre-Emphasis
        5. 7.3.6.5JESD204B Enable
        6. 7.3.6.6Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7Operation in Subclass 0 Systems
      7. 7.3.7Alarm Monitoring
        1. 7.3.7.1NCO Upset Detection
        2. 7.3.7.2Clock Upset Detection
      8. 7.3.8Temperature Monitoring Diode
      9. 7.3.9Analog Reference Voltage
    4. 7.4Device Functional Modes
      1. 7.4.1Dual Channel Mode
      2. 7.4.2Single Channel Mode (DES Mode)
      3. 7.4.3JESD204B Modes
        1. 7.4.3.1JESD204B Output Data Formats
        2. 7.4.3.2Dual DDC and Redundant Data Mode
      4. 7.4.4Power Down Modes
      5. 7.4.5Test Modes
        1. 7.4.5.1Serializer Test-Mode Details
        2. 7.4.5.2PRBS Test Modes
        3. 7.4.5.3Ramp Test Mode
        4. 7.4.5.4Short and Long Transport Test Mode
          1. 7.4.5.4.1Short Transport Test Pattern
          2. 7.4.5.4.2Long Transport Test Pattern
        5. 7.4.5.5D21.5 Test Mode
        6. 7.4.5.6K28.5 Test Mode
        7. 7.4.5.7Repeated ILA Test Mode
        8. 7.4.5.8Modified RPAT Test Mode
      6. 7.4.6Calibration Modes and Trimming
        1. 7.4.6.1Foreground Calibration Mode
        2. 7.4.6.2Background Calibration Mode
        3. 7.4.6.3Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7Offset Calibration
      8. 7.4.8Trimming
      9. 7.4.9Offset Filtering
    5. 7.5Programming
      1. 7.5.1Using the Serial Interface
        1. 7.5.1.1SCS
        2. 7.5.1.2SCLK
        3. 7.5.1.3SDI
        4. 7.5.1.4SDO
        5. 7.5.1.5Streaming Mode
    6. 7.6Register Maps
      1. 7.6.1Memory Map
      2. 7.6.2Register Descriptions
        1. 7.6.2.1 Standard SPI-3.0 (0x000 to 0x00F)
          1. 7.6.2.1.1Configuration A Register (address = 0x000) [reset = 0x30]
          2. 7.6.2.1.2Device Configuration Register (address = 0x002) [reset = 0x00]
          3. 7.6.2.1.3Chip Type Register (address = 0x003) [reset = 0x03]
          4. 7.6.2.1.4Chip ID Register (address = 0x004 to 0x005) [reset = 0x0020]
          5. 7.6.2.1.5Chip Version Register (address = 0x006) [reset = 0x01]
          6. 7.6.2.1.6Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
        2. 7.6.2.2 User SPI Configuration (0x010 to 0x01F)
          1. 7.6.2.2.1User SPI Configuration Register (address = 0x010) [reset = 0x00]
        3. 7.6.2.3 Miscellaneous Analog Registers (0x020 to 0x047)
          1. 7.6.2.3.1Clock Control Register 0 (address = 0x029) [reset = 0x00]
          2. 7.6.2.3.2Clock Control Register 1 (address = 0x02A) [reset = 0x00]
          3. 7.6.2.3.3SYSREF Capture Position Register (address = 0x02C-0x02E) [reset = Undefined]
          4. 7.6.2.3.4INA Full Scale Range Adjust Register (address = 0x030-0x031) [reset = 0xA000]
          5. 7.6.2.3.5INB Full Scale Range Adjust Register (address = 0x032-0x033) [reset = 0xA000]
          6. 7.6.2.3.6Internal Reference Bypass Register (address = 0x038) [reset = 0x00]
          7. 7.6.2.3.7TMSTP+/- Control Register (address = 0x03B) [reset = 0x00]
        4. 7.6.2.4 Serializer Registers (0x048 to 0x05F)
          1. 7.6.2.4.1Serializer Pre-Emphasis Control Register (address = 0x048) [reset = 0x00]
        5. 7.6.2.5 Calibration Registers (0x060 to 0x0FF)
          1. 7.6.2.5.1 Input Mux Control Register (address = 0x060) [reset = 0x01]
          2. 7.6.2.5.2 Calibration Enable Register (address = 0x061) [reset = 0x01]
          3. 7.6.2.5.3 Calibration Configuration 0 Register (address = 0x062) [reset = 0x01]
          4. 7.6.2.5.4 Calibration Status Register (address = 0x06A) [reset = Undefined]
          5. 7.6.2.5.5 Calibration Pin Configuration Register (address = 0x06B) [reset = 0x00]
          6. 7.6.2.5.6 Calibration Software Trigger Register (address = 0x06C) [reset = 0x01]
          7. 7.6.2.5.7 Low-Power Background Calibration Register (address = 0x06E) [reset = 0x88]
          8. 7.6.2.5.8 Calibration Data Enable Register (address = 0x070) [reset = 0x00]
          9. 7.6.2.5.9 Calibration Data Register (address = 0x071) [reset = Undefined]
          10. 7.6.2.5.10Channel A Gain Trim Register (address = 0x07A) [reset = Undefined]
          11. 7.6.2.5.11Channel B Gain Trim Register (address = 0x07B) [reset = Undefined]
          12. 7.6.2.5.12Band-Gap Reference Trim Register (address = 0x07C) [reset = Undefined]
          13. 7.6.2.5.13VINA Input Resistor Trim Register (address = 0x07E) [reset = Undefined]
          14. 7.6.2.5.14VINB Input Resistor Trim Register (address = 0x07F) [reset = Undefined]
          15. 7.6.2.5.15Timing Adjust for A-ADC, Single Channel Mode, Foreground Calibration Register (address = 0x080) [reset = Undefined]
          16. 7.6.2.5.16Timing Adjust for B-ADC, Single Channel Mode, Foreground Calibration Register (address = 0x081) [reset = Undefined]
          17. 7.6.2.5.17Timing Adjust for A-ADC, Single Channel Mode, Background Calibration Register (address = 0x082) [reset = Undefined]
          18. 7.6.2.5.18Timing Adjust for C-ADC, Single Channel Mode, Background Calibration Register (address = 0x083) [reset = Undefined]
          19. 7.6.2.5.19Timing Adjust for C-ADC, Single Channel Mode, Background Calibration Register (address = 0x084) [reset = Undefined]
          20. 7.6.2.5.20Timing Adjust for B-ADC, Single Channel Mode, Background Calibration Register (address = 0x085) [reset = Undefined]
          21. 7.6.2.5.21Timing Adjust for A-ADC, Dual Channel Mode Register (address = 0x086) [reset = Undefined]
          22. 7.6.2.5.22Timing Adjust for C-ADC acting for A-ADC, Dual Channel Mode Register (address = 0x087) [reset = Undefined]
          23. 7.6.2.5.23Timing Adjust for C-ADC acting for B-ADC, Dual Channel Mode Register (address = 0x088) [reset = Undefined]
          24. 7.6.2.5.24Timing Adjust for B-ADC, Dual Channel Mode Register (address = 0x089) [reset = Undefined]
          25. 7.6.2.5.25Offset Adjustment for A-ADC and INA Register (address = 0x08A-0x08B) [reset = Undefined]
          26. 7.6.2.5.26Offset Adjustment for A-ADC and INB Register (address = 0x08C-0x08D) [reset = Undefined]
          27. 7.6.2.5.27Offset Adjustment for C-ADC and INA Register (address = 0x08E-0x08F) [reset = Undefined]
          28. 7.6.2.5.28Offset Adjustment for C-ADC and INB Register (address = 0x090-0x091) [reset = Undefined]
          29. 7.6.2.5.29Offset Adjustment for B-ADC and INA Register (address = 0x092-0x093) [reset = Undefined]
          30. 7.6.2.5.30Offset Adjustment for B-ADC and INB Register (address = 0x094-0x095) [reset = Undefined]
          31. 7.6.2.5.31Offset Filtering Control 0 Register (address = 0x097) [reset = 0x00]
          32. 7.6.2.5.32Offset Filtering Control 1 Register (address = 0x098) [reset = 0x33]
        6. 7.6.2.6 ADC Bank Registers (0x100 to 0x15F)
          1. 7.6.2.6.1 Timing Adjustment for Bank 0 (0° Clock) Register (address = 0x102) [reset = Undefined]
          2. 7.6.2.6.2 Timing Adjustment for Bank 0 (-90° Clock) Register (address = 0x103) [reset = Undefined]
          3. 7.6.2.6.3 Timing Adjustment for Bank 1 (0° Clock) Register (address = 0x112) [reset = Undefined]
          4. 7.6.2.6.4 Timing Adjustment for Bank 1 (-90° Clock) Register (address = 0x113) [reset = Undefined]
          5. 7.6.2.6.5 Timing Adjustment for Bank 2 (0° Clock) Register (address = 0x122) [reset = Undefined]
          6. 7.6.2.6.6 Timing Adjustment for Bank 2 (-90° Clock) Register (address = 0x123) [reset = Undefined]
          7. 7.6.2.6.7 Timing Adjustment for Bank 3 (0° Clock) Register (address = 0x132) [reset = Undefined]
          8. 7.6.2.6.8 Timing Adjustment for Bank 3 (-90° Clock) Register (address = 0x133) [reset = Undefined]
          9. 7.6.2.6.9 Timing Adjustment for Bank 4 (0° Clock) Register (address = 0x142) [reset = Undefined]
          10. 7.6.2.6.10Timing Adjustment for Bank 4 (-90° Clock) Register (address = 0x143) [reset = Undefined]
          11. 7.6.2.6.11Timing Adjustment for Bank 5 (0° Clock) Register (address = 0x152) [reset = Undefined]
          12. 7.6.2.6.12Timing Adjustment for Bank 5 (-90° Clock) Register (address = 0x153) [reset = Undefined]
        7. 7.6.2.7 LSB Control Registers (0x160 to 0x1FF)
          1. 7.6.2.7.1LSB Control Bit Output Register (address = 0x160) [reset = 0x00]
        8. 7.6.2.8 JESD204B Registers (0x200 to 0x20F)
          1. 7.6.2.8.1 JESD204B Enable Register (address = 0x200) [reset = 0x01]
          2. 7.6.2.8.2 JESD204B Mode Register (address = 0x201) [reset = 0x02]
          3. 7.6.2.8.3 JESD204B K Parameter Register (address = 0x202) [reset = 0x1F]
          4. 7.6.2.8.4 JESD204B Manual SYNC Request Register (address = 0x203) [reset = 0x01]
          5. 7.6.2.8.5 JESD204B Control Register (address = 0x204) [reset = 0x02]
          6. 7.6.2.8.6 JESD204B Test Pattern Control Register (address = 0x205) [reset = 0x00]
          7. 7.6.2.8.7 JESD204B DID Parameter Register (address = 0x206) [reset = 0x00]
          8. 7.6.2.8.8 JESD204B Frame Character Register (address = 0x207) [reset = 0x00]
          9. 7.6.2.8.9 JESD204B / System Status Register (address = 0x208) [reset = Undefined]
          10. 7.6.2.8.10JESD204B Channel Power Down Register (address = 0x209) [reset = 0x00]
          11. 7.6.2.8.11JESD204B Extra Lane Enable (Link A) Register (address = 0x20A) [reset = 0x00]
          12. 7.6.2.8.12JESD204B Extra Lane Enable (Link B) Register (address = 0x20B) [reset = 0x00]
        9. 7.6.2.9 Digital Down Converter Registers (0x210-0x2AF)
          1. 7.6.2.9.1 DDC Configuration Register (address = 0x210) [reset = 0x00]
          2. 7.6.2.9.2 Over-range Threshold 0 Register (address = 0x211) [reset = 0xF2]
          3. 7.6.2.9.3 Over-range Threshold 1 Register (address = 0x212) [reset = 0xAB]
          4. 7.6.2.9.4 Over-range Configuration Register (address = 0x213) [reset = 0x07]
          5. 7.6.2.9.5 DDC Configuration Preset Mode Register (address = 0x214) [reset = 0x00]
          6. 7.6.2.9.6 DDC Configuration Preset Select Register (address = 0x215) [reset = 0x00]
          7. 7.6.2.9.7 Digital Channel Binding Register (address = 0x216) [reset = 0x02]
          8. 7.6.2.9.8 Rational NCO Reference Divisor Register (address = 0x217 to 0x218) [reset = 0x0000]
          9. 7.6.2.9.9 NCO Synchronization Register (address = 0x219) [reset = 0x02]
          10. 7.6.2.9.10NCO Frequency (DDC A or DDC B and Preset x) Register (address = see ) [reset = see ]
          11. 7.6.2.9.11NCO Phase (DDC A or DDC B and Preset x) Register (address = see ) [reset = see ]
        10. 7.6.2.10Spin Identification Register (address = 0x297) [reset = Undefined]
      3. 7.6.3SYSREF Calibration Registers (0x2B0 to 0x2BF)
        1. 7.6.3.1SYSREF Calibration Enable Register (address = 0x2B0) [reset = 0x00]
        2. 7.6.3.2SYSREF Calibration Configuration Register (address = 0x2B1) [reset = 0x05]
        3. 7.6.3.3SYSREF Calibration Status Register (address = 0x2B2 to 0x2B4) [reset = Undefined]
        4. 7.6.3.4DEVCLK Aperture Delay Adjustment Register (address = 0x2B5 to 0x2B7) [reset = 0x000000]
        5. 7.6.3.5DEVCLK Timing Adjust Ramp Control Register (address = 0x2B8) [reset = 0x00]
      4. 7.6.4Alarm Registers (0x2C0 to 0x2C2)
        1. 7.6.4.1Alarm Interrupt Register (address = 0x2C0) [reset = Undefined]
        2. 7.6.4.2Alarm Status Register (address = 0x2C1) [reset = 0x1F]
        3. 7.6.4.3Alarm Mask Register (address = 0x2C2) [reset = 0x1F]
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
        1. 8.2.1.1Input Signal Path
        2. 8.2.1.2Clocking
      2. 8.2.2Detailed Design Procedure
        1. 8.2.2.1Calculating Values of AC-Coupling Capacitors
      3. 8.2.3Application Curves
    3. 8.3Initialization Set Up
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Third-Party Products Disclaimer
        1. 11.7Glossary
    2. 11.2Related Links
    3. 11.3Receiving Notification of Documentation Updates
    4. 11.4Community Resources
    5. 11.5Trademarks
    6. 11.6Electrostatic Discharge Caution
    7. 11.7Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

Features

  • ADC Core:
    • 12-bit Resolution
    • Up to 6.4 GSPS in single channel mode
    • Up to 3.2 GSPS in dual channel mode
  • Buffered Analog Inputs with VCMI of 0 V
    • Analog input bandwidth (-3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noise Floor (No signal, VFS = 1.0 VPP):
    • Dual channel mode: -151.8 dBFS/Hz
    • Single channel mode: -154.6 dBFS/Hz
  • Noiseless Aperture Delay (TAD) Adjustment
    • Precise sampling control: 19-fs step
    • Temperature and voltage invariant delays
  • Easy-to-use Synchronization Features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B Serial Data Interface
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital Down-Converters in Dual Channel Mode
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x or 16x decimation
    • Four independent 32-bit NCOs per DDC
  • Power consumption: 3.0 W
  • Power Supplies: 1.1 V, 1.9 V

Applications

  • Communications testers (802.11ad, 5G)
  • Satellite communications (SATCOM)
  • Phased array radar, SIGINT and ELINT
  • Synthetic aperture radar (SAR)
  • Time-of-flight and LIDAR distance measurement
  • Oscilloscopes and wideband digitizers
  • RF sampling software defined radio (SDR)

Description

ADC12DJ3200 is an RF-sampling giga-sample ADC that can directly sample input frequencies from DC to above 10 GHz. In dual channel mode, ADC12DJ3200 can sample up to 3200-MSPS and in single channel mode up to 6400-MSPS. Programmable tradeoffs in channel count (dual channel mode) and Nyquist bandwidth (single channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full power input bandwidth (-3 dB) of 8.0 GHz, with usable frequencies exceeding the -3 dB point in both dual and single channel modes, allows direct RF sampling of L-band, S-band, C-band and X-band for frequency agile systems.

ADC12DJ3200 uses a high speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
ADC12DJ3200FCBGA (144)10.00 mm x 10.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

ADC12DJ3200 Measured Input Bandwidth

ADC12DJ3200 D_BW_1stPage_SLVSD97.gif