ADC12DL3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (LVDS interface) | TI.com

ADC12DL3200 (ACTIVE)

12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (LVDS interface)

 

Description

The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.

Features

  • ADC Core:
    • 12-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Internal Dither for Low-Magnitude, High-Order Harmonics
  • Low-Latency LVDS Interface:
    • Total Latency: < 10 ns
    • Up to 48 Data Pairs at 1.6 Gbps
    • Four DDR Data Clocks
    • Strobe Signals Simplify Synchronization
  • Noise Floor (No Input, VFS = 1.0 VPP-DIFF):
    • Dual-Channel Mode: –151.1 dBFS/Hz
    • Single-Channel Mode: –154.3 dBFS/Hz
  • Buffered Analog Inputs With VCMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: > 10 GHz
    • Full-Scale Input Voltage (VFS, Default): 0.8 VPP
  • Noiseless Aperture Delay (TAD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • Power Consumption: 3.15 W

All trademarks are the property of their respective owners.

View more

Parametrics Compare all products in High-speed ADCs (>10MSPS)

 
Sample Rate (Max) (MSPS)
Features
Resolution (Bits)
Number of input channels
SNR (dB)
ENOB (Bits)
SFDR (dB)
Power consumption (Typ) (mW)
Input range (Vp-p)
Interface
Operating temperature range (C)
Analog input BW (MHz)
Input buffer
Package Group
Package size: mm2:W x L (PKG)
Rating
Architecture
DNL (Typ) (+/-LSB)
INL (Typ) (+/-LSB)
Reference mode
ADC12DL3200 ADC08DJ3200 ADC12DJ2700 ADC12DJ3200
3200
6400    
3200
6400    
2700
5400    
3200
6400    
Ultra High Speed     Ultra High Speed     Ultra High Speed     Ultra High Speed    
12     8     12     12    
2
1    
2
1    
2
1    
2
1    
57.1     49.1     56.7     56.6    
9     7.8     9     9    
70     67
62    
71     67    
3150     2800     2700     3000    
0.8     0.8     0.8     0.8    
DDR LVDS
Parallel LVDS    
JESD204B     JESD204B     JESD204B    
-40 to 85     -40 to 85     -40 to 85     -40 to 85    
8000     8000     8000     8000    
Yes     Yes     Yes     Yes    
FCBGA | 256     FCBGA | 144     FCBGA | 144     FCBGA | 144    
See datasheet (FCBGA)     See datasheet (FCBGA)     See datasheet (FCBGA)     See datasheet (FCBGA)    
Catalog     Catalog     Catalog     Catalog    
Folding Interpolating     Folding Interpolating     Folding Interpolating     Folding Interpolating    
0.3     0.15     0.7
-0.3    
0.3    
2     0.3     2     2.5    
Int     Int     Int     Int