Dual-Channel, 14-Bit, 1.5-GSPS RF-Sampling Analog-to-Digital Converter (ADC)

Dual-Channel, 14-Bit, 1.5-GSPS RF-Sampling Analog-to-Digital Converter (ADC) - ADC32RF42


The ADC32RF42 device is a 14-bit, 1.5-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF42 delivers a noise spectral density of –151.8 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF42 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).


  • 14-Bit, Dual-Channel, 1.5-GSPS ADC
  • Noise Floor: –151.8 dBFS/Hz
  • RF Input Supports Up to 4 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 950 MHz, –2 dBFS):
    • SNR: 61.1 dBFS
    • SFDR: 67-dBc HD2, HD3
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 64-dBc HD2, HD3
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel Up to 12.5 Gbps
  • Power Dissipation: 2 W/Ch at 1.5 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

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Parametrics Compare all products in High Speed ADCs (>10MSPS)

Resolution (Bits)
Sample Rate (Max) (MSPS)
# Input Channels
SNR (dB)
ENOB (Bits)
Power Consumption (Typ) (mW)
Input Range (Vp-p)
Operating Temperature Range (C)
Analog Input BW (MHz)
Input Buffer
Package Group
Package Size: mm2:W x L (PKG)
Reference Mode
14    14    14   
1500    2600    3000   
2    2    2   
61.1    61.2    60.9   
9.8    9.7    9.7   
67    65    67   
4000    5820    6400   
1.35    1.35    1.35   
JESD204B    JESD204B    JESD204B   
-40 to 85    -40 to 85    -40 to 85   
3200    3200    3200   
Yes    Yes    Yes   
72VQFN: 100 mm2: 10 x 10(VQFN)    72VQFN: 100 mm2: 10 x 10(VQFN)    72VQFN: 100 mm2: 10 x 10(VQFN)   
Catalog    Catalog    Catalog   
60    59.8    60.2   
Pipeline    Pipeline    Pipeline   
Int    Int    Int