ADC32RF80 Dual-Channel, 14-Bit, 3-GSPS, RF-Sampling Wideband Receiver and Feedback IC | TI.com

ADC32RF80 (ACTIVE)

Dual-Channel, 14-Bit, 3-GSPS, RF-Sampling Wideband Receiver and Feedback IC

Dual-Channel, 14-Bit, 3-GSPS, RF-Sampling Wideband Receiver and Feedback IC - ADC32RF80
 

Description

The ADC32RF8x (ADC32RF80 and ADC32RF83) is a 14-bit, 3-GSPS, dual-channel telecom receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF8x family delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF8x supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

Features

  • 14-Bit, Dual-Channel, 3-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up to 4.0 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 60.1 dBFS
    • SFDR: 66-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 67-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel at 12.5 Gbps
  • Power Dissipation: 3.2 W/Ch at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

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Parametrics Compare all products in Wideband receivers

 
Number of input channels
Resolution (Bits)
Sample Rate (Max) (MSPS)
Features
Analog Input BW (MHz)
SFDR (Typ) (dB)
SNR (Typ) (dB)
Power Consumption (Typ) (mW)
Logic Voltage DV/DD (Max) (V)
Logic Voltage DV/DD (Min) (V)
Analog Voltage AVDD (Max) (V)
Analog Voltage AVDD (Min) (V)
Operating Temperature Range (C)
ADC32RF80 ADC31RF80 ADC32RF82 ADC32RF83
2     1     2     2    
14     14     14     14    
3000     3000     2456     3000    
Decimating Filter
Ultra High Speed    
Decimating Filter
Ultra High Speed    
Decimating Filter
Ultra High Speed    
Decimating Filter
Ultra High Speed    
3200     3200     3200     3200    
66     71     67     66    
61.1     61.4     61.2     61.1    
6400     3200     5500     6400    
1.2     1.2     1.2     1.2    
1.1     1.1     1.1     1.1    
1.25
2    
1.25
2    
1.25
2    
1.25
2    
1.1
1.8    
1.1
1.8    
1.1
1.8    
1.1
1.8    
-40 to 85     -40 to 85     -40 to 85     -40 to 85