Quad Channel 16-Bit, 100-MSPS 84.6dB SNR ADC - ADS5263

ADS5263 (ACTIVE)

Quad Channel 16-Bit, 100-MSPS 84.6dB SNR ADC

Recommended alternative parts

  • ADS5562  - The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.   16-bit, 1-channel, 80 MSPS, 84.3 SNR
  • ADS6444  - The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.   14-bit, 4-channel, 105 MSPS, 73 SNR

Description

Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.

The device also has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode.

The ADS5263 has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate.

The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers.

The data from each channel ADC is serialized and output on two pairs of LVDS output lines, along with a bit clock and a frame clock. Serial LVDS outputs reduce the number of interface lines. This, together with the low-power design, enables four channels to be packaged in a compact 9-mm × 9-mm QFN, allowing high system integration densities.

In order to ease interfacing to CCD sensors, a clamp function is integrated in the device. Using this feature, the analog input pins can be clamped to an internal voltage, based on a SYNC signal. With this, the CCD sensor output can be easily ac-coupled to the ADS5263 analog inputs. The clamp feature and quad channels in a compact package make the ADS5263 attractive for industrial CCD imaging applications.

The device integrates an internal reference trimmed to accurately match across devices. Additionally, the device supports an external reference mode for applications that require very low temperature drift of reference. The ADS5263 is available in a non-magnetic QFN package that does not create any MRI signature. The device is specified over the full industrial temperature range.

Features

  • Maximum Sample Rate: 100 MSPS
  • Programmable Device Resolution
    • Quad-Channel, 16-Bit,
      High-SNR Mode
    • Quad-Channel, 14-Bit, Low-Power Mode
  • 16-Bit High-SNR Mode
    • 1.4 W Total Power at 100 MSPS355 mW / Channel
    • 4 Vpp Full-scale Input
    • 85-dBFS SNR at fin = 3 MHz, 100 MSPS
  • 14-Bit Low-Power Mode
    • 785 mW Total Power at 100 MSPS195 mW/Channel
    • 2-Vpp Full-Scale Input
    • 74-dBFS SNR at fin = 10 MHz
    • Integrated Clamp (for interfacing to CCD sensors)
  • Low-Frequency Noise Suppression
  • Digital Processing Block
    • Programmable FIR Decimation Filters
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-Channel Averaging
  • Programmable Mapping Between ADC Input Channels and LVDS
    Output Pins—Eases Board Design
  • Variety of Test Patterns to Verify Data Capture by
    FPGA/Receiver
  • Serialized LVDS Outputs
  • Internal and External References
  • 3.3-V Analog Supply
  • 1.8-V Digital Supply
  • Recovers From 6-dB Overload Within 1 Clock Cycle
  • Package:
    • 9-mm × 9-mm 64-Pin QFN
    • Non-magnetic package option for MRI
      systems
  • CMOS Technology

View more

Parametrics Compare all products in High Speed ADC (>10MSPS)

 
Resolution (Bits)
Sample Rate (max) (SPS)
# Input Channels
SNR (dB)
ENOB (Bits)
SFDR (dB)
SINAD (dB)
Power Consumption (Typ) (mW)
Analog Input BW (MHz)
Architecture
DNL (Max) (+/-LSB)
INL (Max) (+/-LSB)
Digital Supply (Min) (V)
Digital Supply (Max) (V)
Analog Voltage AV/DD (Min) (V)
Analog Voltage AV/DD (Max) (V)
Reference Mode
Input Range
Interface
Rating
Operating Temperature Range (C)
Approx. Price (US$)
ADS5263 ADS5560 ADS5562
16     16     16    
100MSPS     40MSPS     80MSPS    
4     1     1    
84.6     84.3     84    
12.7     13.5     13.1    
80     90     85    
77.5     83.2     80.5    
1350     674     865    
70     250     250    
Pipeline     Pipeline     Pipeline    
0.1     0.95     0.95    
  8.5     8.5    
1.7     3     3    
1.9     3.6     3.6    
3     3     3    
3.6     3.6     3.6    
Int
Ext    
Int
Ext    
Int
Ext    
4V (p-p)     3.6V (p-p)     3.6V (p-p)    
Parallel LVDS     Parallel LVDS
Serial SPI Interface    
Parallel LVDS
Serial SPI Interface    
Catalog     Catalog     Catalog    
-40 to 85     -40 to 85     -40 to 85    
236.50 | 1ku     34.97 | 1ku     48.35 | 1ku    

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