Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter (ADC) - ADS54J60

ADS54J60 (ACTIVE)

Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter (ADC)

 

Description

The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.

Features

  • 16-Bit Resolution, Dual-Channel, 1-GSPS ADC
  • Noise Floor: –159 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 70 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 86 dBc (Including Interleaving Tones)
    • SFDR: 89 dBc (Except HD2, HD3, and Interleaving Tones)
  • Spectral Performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 67.5 dBFS
    • NSD: –154.5 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (Except HD2, HD3, and Interleaving Tones)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Wideband DDC Block
  • JESD204B Interface with Subclass 1 Support:
    • 2 Lanes per ADC at 10.0 Gbps
    • 4 Lanes per ADC at 5.0 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 1.35 W/ch at 1 GSPS
  • VQFNP-72 Package (10 mm × 10 mm)

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Parametrics Compare all products in High Speed ADCs (>10MSPS)

 
Resolution (Bits)
Sample Rate (Max) (MSPS)
# Input Channels
SNR (dB)
ENOB (Bits)
SFDR (dB)
Power Consumption (Typ) (mW)
Input Range (Vp-p)
Interface
Operating Temperature Range (C)
Analog Input BW (MHz)
Input Buffer
Package Group
Package Size: mm2:W x L (PKG)
Rating
SINAD (dB)
Architecture
Reference Mode
ADS54J60 ADS54J20 ADS54J40 ADS54J42 ADS54J64 ADS54J66 ADS54J69
16    12    14    14    14    14    16   
1000    1000    1000    625    1000
500   
500    500   
2    2    2    2    4    4    2   
70    67.8    69    71    69    70.8    73   
11.6    10.9    11.2    11.5    11.6    11.4    12.1   
86    86    86    85    86    89    91   
2700    2700    2700    1940    2500    2700    2700   
1.9    1.9    1.9    1.9    1.1    1.9    1.9   
JESD204B    JESD204B    JESD204B    JESD204B    JESD204B    JESD204B    JESD204B   
-40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85   
1200    1200    1200    1200    1000    900    1200   
Yes    Yes    Yes    Yes    Yes    Yes    Yes   
VQFN    VQFN    VQFN    VQFN    VQFN    VQFN    VQFN   
72VQFN: 100 mm2: 10 x 10(VQFN)    72VQFN: 100 mm2: 10 x 10(VQFN)    72VQFN: 100 mm2: 10 x 10(VQFN)    72VQFN: 100 mm2: 10 x 10(VQFN)    72VQFN: 100 mm2: 10 x 10(VQFN)    72VQFN: 100 mm2: 10 x 10(VQFN)    72VQFN: 100 mm2: 10 x 10(VQFN)   
Catalog    Catalog    Catalog    Catalog    Catalog    Catalog    Catalog   
70.8    68.3    69.3    70.8    73    73.9    73   
Pipeline    Pipeline    Pipeline    Pipeline    Pipeline    Pipeline    Pipeline   
Int    Int    Int    Int    Int    Int    Int   

WEBENCH® Designer ADS54J60

Tx:
Mid Channel:
Rx:
Max Data Rate:  Gbps

 
Number of UI:
PRBS:
 
Eye Diagram