SLUSC51C April 2015  – November 2016

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Supply Current
    6. 6.6 VP 5.3-V Supply Regulation Voltage
    7. 6.7 VDD18 1.8-V Internal Digital Supply
    8. 6.8 V5VAO Analog Supply
    9. 6.9 VM -5-V Integrated Charge Pump
    10. 6.10Analog-to-Digital Converter (ADC): Analog Front End
    11. 6.11ADC: VSENSEn Cell Measurement Inputs
    12. 6.12ADC: VMODULE Input
    13. 6.13ADC: Post Board Assembly: VSENSEn Cell Measurement Inputs
    14. 6.14ADC: AUXn General Purpose Inputs
    15. 6.15ADC: Internal Temperature Measurement and Thermal Shutdown (TSD)
    16. 6.16Passive Balancing Control Outputs
    17. 6.17Digital Input/Output: VIO-Based Single-Ended I/O
    18. 6.18Digital Input/Output: Daisy Chain Vertical Bus
    19. 6.19Digital Input/Output: Wakeup
    20. 6.20EEPROM
    21. 6.21Secondary Protector - Window Comparators
    22. 6.22Power-On-Reset (POR) and FAULT Flag Thresholds
    23. 6.23Miscellaneous
    24. 6.24Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 Block Descriptions
        1. 7.3.1.1Power
          1. 7.3.1.1.1TOP Pin Connection
          2. 7.3.1.1.2V10VAO
          3. 7.3.1.1.3V5VAO
          4. 7.3.1.1.4VP Regulated Output
          5. 7.3.1.1.5VDIG Power Input
          6. 7.3.1.1.6VDD18 Regulator
          7. 7.3.1.1.7VIO Power Input
          8. 7.3.1.1.8VM Charge Pump
      2. 7.3.2 Analog Front End (AFE)/Level Shifter
      3. 7.3.3 ADC
        1. 7.3.3.1 Channel Selection Registers
        2. 7.3.3.2 Averaging
        3. 7.3.3.3 Recommended Sample Periods
        4. 7.3.3.4 VSENSE Input Channels
        5. 7.3.3.5 AUXn Input Channels
        6. 7.3.3.6 VMODULE Measurement Result Conversion to Voltage
        7. 7.3.3.7 Digital Die Temperature Measurement
          1. 7.3.3.7.1Automatic Temperature Sampling
        8. 7.3.3.8 Analog Die Temperature Measurement
        9. 7.3.3.9 VM Measurement Result Conversion to Voltage
        10. 7.3.3.10V5VAO, VDIG, VDD18 Measurement Result Conversion to Voltage
        11. 7.3.3.11Auto-Monitor
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 Voltage Reference (ADC)
      6. 7.3.6 Voltage Reference (REF2)
      7. 7.3.7 Passive Balancing
      8. 7.3.8 General Purpose Input-Outputs (GPIO)
      9. 7.3.9 UART Interface to Host Microcontroller
        1. 7.3.9.1UART Transmitter
        2. 7.3.9.2UART Receiver
        3. 7.3.9.3Baud Rate Selection
        4. 7.3.9.4Communication Clear (Break) Detection
        5. 7.3.9.5Communication Reset Detection
        6. 7.3.9.6Communication Timeouts
          1. 7.3.9.6.1Communications Timeout Fault
          2. 7.3.9.6.2Communications Timeout Power-Down (SHUTDOWN)
      10. 7.3.10Stacked Daisy-Chain Communications
        1. 7.3.10.1Differential Communications
        2. 7.3.10.2Protocol Description
      11. 7.3.11Register and EEPROM
        1. 7.3.11.1Error Check and Correct (ECC) EEPROM
      12. 7.3.12FAULT Sensing and Signaling
        1. 7.3.12.1 Fault Flow Schematics
        2. 7.3.12.2 FAULT Signaling
        3. 7.3.12.3 Fault Sensing
          1. 7.3.12.3.1Fault Output Control
          2. 7.3.12.3.2Fault Masking
        4. 7.3.12.4 Fault Latching
          1. 7.3.12.4.1Special Considerations in Unlatched Fault Mode
        5. 7.3.12.5 Fault Status and Fault Reset
        6. 7.3.12.6 Checksum Faults
          1. 7.3.12.6.1Checksum Testing
            1. 7.3.12.6.1.1Computing User Checksum
        7. 7.3.12.7 AUXn OV/UV Threshold Faults
        8. 7.3.12.8 Secondary Protectors: Analog Window Comparators for Cell UV/OV
          1. 7.3.12.8.1Window Comparator Special Considerations
        9. 7.3.12.9 Communications Faults
        10. 7.3.12.10Communications Timeout Counters
      13. 7.3.13Built-in-Test Functions
        1. 7.3.13.1Safety Manual and FMEDA
    4. 7.4Device Functional Modes
      1. 7.4.1SHUTDOWN
      2. 7.4.2Wakeup
      3. 7.4.3Wakeup Behavior from SHUTDOWN
      4. 7.4.4Power-On Reset (POR) or Wakeup
      5. 7.4.5Calculating Wakeup Timing
      6. 7.4.6Soft Reset
      7. 7.4.7Wakeup Behavior in IDLE Mode
    5. 7.5Command and Response Protocol
      1. 7.5.1Transaction Frame Description
        1. 7.5.1.1Frame Initialization Byte
        2. 7.5.1.2Device Address/Group ID Byte
        3. 7.5.1.3Register Address Byte(s)
        4. 7.5.1.4Data Bytes
        5. 7.5.1.5CRC Bytes
      2. 7.5.2CRC Description
      3. 7.5.3Transaction Frame Examples
        1. 7.5.3.1Single Device Write with Response Command Frame
          1. 7.5.3.1.1Single Device Write with Response to Command Register (Address 2)
            1. 7.5.3.1.1.1Data Contains Command Only
            2. 7.5.3.1.1.2Data Contains Command and Channel Selection
            3. 7.5.3.1.1.3Data Contains Command, Channel Selection, and Averaging Selection
          2. 7.5.3.1.2Single Device Write with Response to Register(s) Other than Command Register
            1. 7.5.3.1.2.1Requesting Four Bytes of Data from a Single Register
            2. 7.5.3.1.2.2Requesting Multiple Bytes across Register Boundaries
        2. 7.5.3.2Single Device Write without Response Command Frame
        3. 7.5.3.3Group_Write_With_Response Command Frame
          1. 7.5.3.3.1Configuration 1: Group Write with Response to Command Register with Sampling Parameters Included in Command Frame
          2. 7.5.3.3.2Configuration 2: Group Write with Response to Command Register without Sampling Parameters Included in Command Frame
          3. 7.5.3.3.3Configuration 3: Group Write with Response to non-Command Register
          4. 7.5.3.3.4Configuration 4: Group Write with Response to Non-Command Register
        4. 7.5.3.4Group Write without Response Command Frame
        5. 7.5.3.5Broadcast Write with Response Command Frame
        6. 7.5.3.6Broadcast Write without Response Command Frame
      4. 7.5.4Response Frame
    6. 7.6Register Maps
      1. 7.6.1Conventions and Notations
        1. 7.6.1.1Register Usage
      2. 7.6.2Register Summary
      3. 7.6.3Register Details
        1. 7.6.3.1 SREV 0x00-01 (0-1) Device Version
        2. 7.6.3.2 CMD 0x02 (2) Command
        3. 7.6.3.3 CHANNELS 0x03-06 (3-6) Channel Select
        4. 7.6.3.4 OVERSMPL 0x07 (7) Command Oversampling
        5. 7.6.3.5 ADDR 0x0A (10) Device Address
        6. 7.6.3.6 GROUP_ID 0x0B (11) Group ID
        7. 7.6.3.7 DEV_CTRL 0x0C (12) Device Control
        8. 7.6.3.8 NCHAN 0x0D (13) Number of Channels
        9. 7.6.3.9 DEVCONFIG 0x0E (14) Device Configuration
        10. 7.6.3.10PWRCONFIG (0x0F) (15) Power Configuration
        11. 7.6.3.11COMCONFIG 0x10-11 (16-17) Communications Configuration
        12. 7.6.3.12 TXHOLDOFF 0x12 (18) UART Transmitter Holdoff
        13. 7.6.3.13 CBCONFIG 0x13 (19) Balance Configuration
        14. 7.6.3.14CBENBL 0x14-15 (20-21) Balancing Enable
        15. 7.6.3.15TSTCONFIG 0x1E-1F (30-31) Test Configuration
        16. 7.6.3.16TESTCTRL 0x20-21 (32-33) Test Control
        17. 7.6.3.17TEST_ADC 0x22-24 (34-36) ADC Output Test
        18. 7.6.3.18TESTAUXPU 0x25 (37) AUX Pull-up Test Control
        19. 7.6.3.19CTO 0x28 (40) Communication Timeout
        20. 7.6.3.20CTO_CNT 0x29-2B (41-43) Communication Timeout Counter
        21. 7.6.3.21AM_PER 0x32 (50) Auto-Monitor Period
        22. 7.6.3.22AM_CHAN 0x33-36 (51-54) Auto-Monitor Channel Select
        23. 7.6.3.23AM_OSMPL 0x37 (55) Auto-Monitor Oversampling
        24. 7.6.3.24SMPL_SLY1 0x3D (61) Initial Sampling Delay
        25. 7.6.3.25Cell_CSPER 0x3E (62) Cell Voltage and Internal Temperature Sampling Interval
        26. 7.6.3.26AUX_SPER 0x3F-42 (63-66) AUX Sampling Period
        27. 7.6.3.27TEST_SPER 0x43-44 (67-68) Test Sampling Periods
        28. 7.6.3.28SHDN_STS 0x50 (80) Shutdown Recovery Status
        29. 7.6.3.29STATUS 0x51 (81) Device Status
        30. 7.6.3.30FAULT_SUM 0x52-53 (82-83) Fault Summary
        31. 7.6.3.31FAULT_UV 0x54-55 (84-85) Cell Undervoltage Fault
        32. 7.6.3.32FAULT_OV 0x56-57 (86-87) Cell Overvoltage Fault
        33. 7.6.3.33FAULT_AUX 0x58-59 (88-89) Auxiliary Under/Over-Threshold Fault
        34. 7.6.3.34FAULT_2UV 0x5A-5B (90-91) Comparator Undervoltage Fault
        35. 7.6.3.35FAULT_2OV 0x5C-5D (92-93) Comparator Overvoltage Fault
        36. 7.6.3.36FAULT_COM 0x5E-5F (94-95) Communications Fault
        37. 7.6.3.37FAULT_SYS 0x60 (96) System Fault
        38. 7.6.3.38FAULT_DEV 0x61-62 (97-98) Chip Fault
        39. 7.6.3.39FAULT_GPI 0x63 (99) GPI Fault
        40. 7.6.3.40MASK_COMM 0x68-69 (104-105) Communications Fault Masks
        41. 7.6.3.41MASK_SYS 0x6A (106) System Fault Masks
        42. 7.6.3.42MASK_DEV 0x6B-6C (107-108) Chip Fault Masks
        43. 7.6.3.43FO_CTRL 0x6E-6F (110-111) Fault Output Control
        44. 7.6.3.44GPIO_DIR 0x78 (120) General Purpose IO Direction
        45. 7.6.3.45GPIO_OUT 0x79 (121) General Purpose Output
        46. 7.6.3.46GPIO_PU 0x7A (122) General Purpose Pull-Up
        47. 7.6.3.47GPIO_PD 0x7B (123) General Purpose Pull-Down
        48. 7.6.3.48GPIO_IN 0x7C (124) General Purpose Input
        49. 7.6.3.49GP_FLT_IN 0x7D (125) General Purpose Fault Input
        50. 7.6.3.50MAGIC1 0x82-85 (130-133) Magic1
        51. 7.6.3.51COMP_UV 0x8C (140) Comparator Undervoltage Threshold
        52. 7.6.3.52COMP_OV 0x8D (141) Comparator Overvoltage Threshold
        53. 7.6.3.53CELL_UV 0x8E-8F (142-143) Cell Undervoltage Threshold
        54. 7.6.3.54CELL_OV 0x90-91 (144-145) Cell Overvoltage Threshold
        55. 7.6.3.55AUX0_UV 0x92-93 (146-147) AUX0 Undervoltage Threshold
        56. 7.6.3.56AUX0_OV 0x94-95 (148-149) AUX0 Overvoltage Threshold
        57. 7.6.3.57AUX1_UV 0x96-97 (150-151) AUX1 Undervoltage Threshold
        58. 7.6.3.58AUX1_OV 0x98-99 (152-153) AUX1 Overvoltage Threshold
        59. 7.6.3.59AUX2_UV 0x9A-9B (154-155) AUX2 Undervoltage Threshold
        60. 7.6.3.60AUX2_OV 0x9C-9D (156-157) AUX2 Overvoltage Threshold
        61. 7.6.3.61AUX3_UV 0x9E-9F (158-159) AUX3 Undervoltage Threshold
        62. 7.6.3.62AUX3_OV 0xA0-A1 (160-161) AUX3 Overvoltage Threshold
        63. 7.6.3.63AUX4_UV 0xA2-A3 (162-163) AUX4 Undervoltage Threshold
        64. 7.6.3.64AUX4_OV 0xA4-A5 (164-165) AUX4 Overvoltage Threshold
        65. 7.6.3.65AUX5_UV 0xA6-A7 (166-167) AUX5 Undervoltage Threshold
        66. 7.6.3.66AUX5_OV 0xA8-A9 (168-169) AUX5 Overvoltage Threshold
        67. 7.6.3.67AUX6_UV 0xAA-AB (170-171) AUX6 Undervoltage Threshold
        68. 7.6.3.68AUX6_OV 0xAC-AD (172-173) AUX6 Overvoltage Threshold
        69. 7.6.3.69AUX7_UV 0xAE-AFB (174-175) AUX7 Undervoltage Threshold
        70. 7.6.3.70AUX7_OV 0xB0-B1 (176-177) AUX7 Overvoltage Threshold
        71. 7.6.3.71LOT_NUM 0xBE-C5 (190-197) Device Lot Number
        72. 7.6.3.72SER_NUM 0xC6-C7 (198-199) Device Serial Number
        73. 7.6.3.73SCRATCH 0xC8-CF (200-207) Scratch Registers
        74. 7.6.3.74VSOFFSET 0xD2 (210) Cell Offset Correction
        75. 7.6.3.75VSGAIN 0xD3 (211) Cell Gain Correction
        76. 7.6.3.76AX0OFFSET 0xD4-D5 (212-213) AUX0 Offset Correction
        77. 7.6.3.77AX1OFFSET 0xD6-D7 (214-215) AUX1 Offset Correction
        78. 7.6.3.78AX2OFFSET 0xD8-D9 (216-217) AUX2 Offset Correction
        79. 7.6.3.79AX3OFFSET 0xDA-DB (218-219) AUX3 Offset Correction
        80. 7.6.3.80AX4OFFSET 0xDC-DD (220-221) AUX4 Offset Correction
        81. 7.6.3.81AX5OFFSET 0xDE-DF (222-223) AUX5 Offset Correction
        82. 7.6.3.82AX6OFFSET 0xE0-E1 (224-225) AUX6 Offset Correction
        83. 7.6.3.83AX7OFFSET 0xE2-E3 (226-227) AUX7 Offset Correction
        84. 7.6.3.84TSTR_ECC 0xE6-ED (230-237) ECC Test Result[1:0]
        85. 7.6.3.85CSUM 0xF0-F3 (240-243) Checksum
        86. 7.6.3.86CSUM_RSLT 0xF4-F7(244-247) Checksum Readout
        87. 7.6.3.87TEST_CSUM 0xF8-F9 (248-249) Checksum Test Result
        88. 7.6.3.88EE_BURN 0xFA (250) EEPROM Burn Count
        89. 7.6.3.89MAGIC2 0xFC-FF (252-255) Magic2
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1Special Pin Considerations
        1. 8.1.1.1Unused VSENSE Inputs (Designs with Less Than 16 Cells)
        2. 8.1.1.2Unused AUX Inputs
        3. 8.1.1.3TOP and VSENSE16 Pins
        4. 8.1.1.4AGND1 and VSENSE0 Pins
        5. 8.1.1.5VSENSE to VSENSE Connections
        6. 8.1.1.6AUX_Connections
      2. 8.1.2Communication Buses
        1. 8.1.2.1Single-Ended Communication (UART)
        2. 8.1.2.2Daisy-Chain Communication Differential Communications
          1. 8.1.2.2.1Stacked Devices on Same PCB
          2. 8.1.2.2.2Stacked Devices Separated by Cables
          3. 8.1.2.2.3Daisy-Chain Communication Cables
          4. 8.1.2.2.4TVS Diodes
          5. 8.1.2.2.5Resistance
          6. 8.1.2.2.6Common-Mode Filter
          7. 8.1.2.2.7Isolation Capacitor
          8. 8.1.2.2.8Unused Differential Communications Pins
      3. 8.1.3ADC
        1. 8.1.3.1Idle (Parking) Channel Errors
        2. 8.1.3.2VSENSE Channel Post-Assembly Calibration Adjustment
          1. 8.1.3.2.1Gain Error Correction
          2. 8.1.3.2.2Offset Error Correction
        3. 8.1.3.3AUX Channel Post-Assembly Calibration Adjustment
      4. 8.1.4Device Addressing
        1. 8.1.4.1Using a Stored Address
        2. 8.1.4.2GPIO Addressing
        3. 8.1.4.3Auto Addressing
      5. 8.1.5Auto-Monitor Function
      6. 8.1.6Balancing
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
        1. 8.2.2.1Voltage Reference
        2. 8.2.2.2OUT1 Capacitor Selection
          1. 8.2.2.2.1For OVERSMPL[CMD_OVS_CYCLE] = 0
          2. 8.2.2.2.2For OVERSMPL[CMD_OVS_CYCLE] = 1
        3. 8.2.2.3Passive Cell Balancing Circuit
        4. 8.2.2.4Balance FET
        5. 8.2.2.5Balance Resistor
        6. 8.2.2.6WAKEUP Pin
      3. 8.2.3Application Curves
    3. 8.3Initialization Set Up
      1. 8.3.1Factory Configuration Summary
      2. 8.3.2Device Setup/User Configuration Summary
  9. Power Supply Recommendations
    1. 9.1NPN LDO Supply
      1. 9.1.1External Supply
      2. 9.1.2Handling of Supplies in Shutdown Mode
      3. 9.1.3AFE Output RC Filter
  10. 10Layout
    1. 10.1Layout Guidelines
      1. 10.1.1Grounding
      2. 10.1.2Differential Communications
    2. 10.2Layout Example
    3. 10.3Board Construction and Accuracy
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Development Support
      2. 11.1.2Device-Specific Terminology
    2. 11.2Documentation Support
      1. 11.2.1Related Documentation
    3. 11.3Receiving Notification of Documentation Updates
    4. 11.4Community Resources
    5. 11.5Trademarks
    6. 11.6Electrostatic Discharge Caution
    7. 11.7Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Features

  • Monitors and Balances 6-to-16 Cells per Device
  • Highly Accurate Monitoring
    • High Performance 14-bit Analog-to-Digital Converter (ADC) With Internal Reference
    • All Cells Converted in 2.4 ms (Nominal)
    • Eight AUX Inputs for Temperature and Other Sensors with Input Voltage of 0 V to 5 V
    • Internal Precision Reference
  • Integrated Protector With Separate Vref for Overvoltage (OV) and Undervoltage (UV) Comparators and Programmable VCELL Set Points
  • Engineered for High System Robustness
    • Up to 1-Mb/s Stackable Isolated Differential-UART
    • Up to 16 ICs in Daisy-Chain With Twisted Pair
    • Passes Bulk Current Injection (BCI) Test
    • Designed for Robust Hot-Plug Performance
  • Passive Balancing with External n-FETs and Active Balancing with EMB1428Q/EMB1499Q
  • Can Help Customers Meet Functional Safety Standard Requirements (For Example, ISO26262)
    • Built-in Self-Tests to Validate Defined Internal Functions
    • Support for Open Wire Detection
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C3

Applications

  • Electric and Hybrid Electric Vehicles (EV, HEV, PHEV, Mild Hybrid)
  • 48-V Systems (Single-Chip Solution)
  • Energy Storage (ESS) and UPS
  • E-Bikes, E-Scooters

Description

The bq76PL455A-Q1 device is an integrated 16-cell battery monitoring and protection device, designed for high-reliability automotive applications. The integrated high-speed, differential, capacitor-isolated communications interface allows up to sixteen bq76PL455A-Q1 devices to communicate with a host via a single high-speed Universal Asynchronous Receiver/Transmitter (UART) interface.

The bq76PL455A-Q1 monitors and detects several different fault conditions, including: overvoltage, undervoltage, overtemperature, and communication faults. Six GPIO ports as well as eight analog AUX ADC inputs are included for additional monitoring and programmable functionality. A secondary thermal shutdown is included for further protection.

The bq76PL455A-Q1 has features that customers may find useful to help them meet functional safety standard requirements. See Safety Manual for bq76PL455A-Q1 (SLUUB67).

Device Information(1)

PART NUMBER PACKAGEBODY SIZE (NOM)
bq76PL455A-Q1TQFP (80) 12.00 mm × 12.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

bq76PL455A-Q1 Typ_Use_Pg1.gif