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CD4021B-Q1

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Automotive Catalog CMOS 8-Stage Static Shift Register

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Data sheet

CD4021B-Q1

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Data sheet Order now

Product details

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 8.5 IOL (max) (mA) 4.2 IOH (max) (mA) -4.2 Supply current (max) (µA) 3000 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -40 to 125 Rating Automotive
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 8.5 IOL (max) (mA) 4.2 IOH (max) (mA) -4.2 Supply current (max) (µA) 3000 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -40 to 125 Rating Automotive
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Qualified for Automotive Applications
  • Medium-Speed Operation: 12-MHz (Typ) Clock Rate at VDD – VSS = 10 V
  • Fully Static Operation
  • Eight Master-Slave Flip-Flops Plus Output Buffering and Control Gating
  • 100% Tested for Quiescent Current at 20 V
  • Maximum Input Current of 1 µA at 18 V Over Full Package-Temperature Range:
    100 nA at 18 V and 25°C
  • Noise Margin (Full Package-Temperature Range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Standardized Symmetrical Output Characteristics
  • 5-V, 10-V, and 15-V Parametric Ratings
  • Meets All Requirements of JEDEC Tentative Standard No. 13B,
    "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Latch-Up Performance Meets 50 mA per JESD 78, Class I
  • APPLICATIONS
    • Parallel Input/Serial Output Data Queuing
    • Parallel-to-Serial Data Conversion
    • General-Purpose Register
  • Qualified for Automotive Applications
  • Medium-Speed Operation: 12-MHz (Typ) Clock Rate at VDD – VSS = 10 V
  • Fully Static Operation
  • Eight Master-Slave Flip-Flops Plus Output Buffering and Control Gating
  • 100% Tested for Quiescent Current at 20 V
  • Maximum Input Current of 1 µA at 18 V Over Full Package-Temperature Range:
    100 nA at 18 V and 25°C
  • Noise Margin (Full Package-Temperature Range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Standardized Symmetrical Output Characteristics
  • 5-V, 10-V, and 15-V Parametric Ratings
  • Meets All Requirements of JEDEC Tentative Standard No. 13B,
    "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Latch-Up Performance Meets 50 mA per JESD 78, Class I
  • APPLICATIONS
    • Parallel Input/Serial Output Data Queuing
    • Parallel-to-Serial Data Conversion
    • General-Purpose Register

CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.

The CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).

CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.

The CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
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Type Title Date
* Data sheet CD4021B-Q1 CMOS 8-Stage Static Shift Register datasheet 26 Mar 2010
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
More literature Automotive Logic Devices Brochure 27 Aug 2014
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 03 Dec 2001

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The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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