CD4075B CMOS Triple 3-Input OR Gate | TI.com

CD4075B (ACTIVE)

CMOS Triple 3-Input OR Gate

CMOS Triple 3-Input OR Gate - CD4075B
Datasheet
 

Description

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.

The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Features

  • Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Standardized, symmetrical output characteristics
  • Noise margin (full package-temperature range):
         1 V at VDD = 5 V
         2 V at VDD = 10 V
      2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

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Parametrics Compare all products in OR gate

 
Technology Family
VCC (Min) (V)
VCC (Max) (V)
Channels (#)
Inputs per channel
ICC @ Nom Voltage (Max) (mA)
IOL (Max) (mA)
IOH (Max) (mA)
Input Type
Output Type
Features
Data Rate (Max) (Mbps)
Rating
Operating Temperature Range (C)
Package Group
Package Size: mm2:W x L (PKG)
CD4075B
CD4000    
3    
18    
3    
3    
0.015    
6.8    
-6.8    
Standard CMOS    
Push-Pull    
Standard Speed (tpd > 50ns)    
8    
Catalog    
-55 to 125    
PDIP | 14
SOIC | 14
SO | 14
TSSOP | 14    
See datasheet (PDIP)
14SO: 80 mm2: 7.8 x 10.2 (SO | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)