High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latches

High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latches - CD74HC75


The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.


  • True and Complementary Outputs
  • Buffered Inputs and Outputs
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

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Parametrics Compare all products in Other Latch

Technology Family
VCC (Min) (V)
VCC (Max) (V)
Bits (#)
Voltage (Nom) (V)
F @ Nom Voltage (Max) (Mhz)
ICC @ Nom Voltage (Max) (mA)
tpd @ Nom Voltage (Max) (ns)
Output Drive (IOL/IOH) (Max) (mA)
3-State Output
Operating Temperature Range (C)
CD74HC75 CD54HC75
HC    HC   
2    2   
6    6   
4    4   
6    6   
28    28   
0.04    0.04   
24    24   
5.2/-5.2    5.2/-5.2   
No    No   
Catalog    Military   
-55 to 125    -55 to 125   

Other qualified versions of CD74HC75

Version Part Number Definition
Military CD54HC75 QML certified for Military and Defense Applications