产品详情

Function Clock generator Number of outputs 2 Output frequency (max) (MHz) 1175 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog
Function Clock generator Number of outputs 2 Output frequency (max) (MHz) 1175 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog
VQFN (RHB) 32 25 mm² 5 x 5
  • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter
  • Fully Configurable Outputs Including Frequency and Output Format
  • Smart Input Multiplexer Automatically Switches Between One of Two Reference Inputs
  • Multiple Operational Modes Include Clock Generation Through Crystal, SERDES Start-Up Mode, Jitter Cleaning, and Oscillator Based Holdover Mode
  • Integrated EEPROM Determines Device Configuration at Power Up
  • Excellent Jitter Performance
  • Integrated Frequency Synthesizer Including PLL, Multiple VCOs, and Loop Filter:
    • Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode
    • Programmable Charge Pump Gain and Loop Filter Settings
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz to 2.356 GHz.
  • Universal Output Blocks Support Up to 2 Differential, 4 Single-Ended, or Combinations of Differential or Single-Ended:
    • 0.5 ps RMS (10 kHz to 20 MHz) Output Jitter Performance
    • Low Output Phase Noise: –130 dBc/Hz at 1 MHz Offset, Fc = 491.52 MHz
    • Output Frequency Ranges From 10.94 MHz to 1.175 GHz in Synthesizer Mode
    • LVPECL, LVDS, and LVCMOS
    • Independent Output Dividers Support Divide Ratios for 1, 2, 3, 4, 5, 8, 10, 12, 16, 20, 24, and 32
  • Flexible Inputs With Innovative Smart Multiplexer:
    • Two Universal Differential Inputs Accept Frequencies from 1 MHz up to 500 MHz (LVPECL), 500 MHz (LVDS), or 250 MHz (LVCMOS)
    • One Auxiliary Input Accepts Crystals in the Range of 2 MHz to 42 MHz
    • Clock Generator Mode Using Crystal Input
    • Smart Input Multiplexer Can be Configured to Automatically Switch Between Highest Priority Clock Source Available Allowing for Fail-Safe Operation
  • Typical Power Consumption 750 mW at 3.3 V
  • Integrated EEPROM Stores Default Settings; Therefore, the Device Can Power Up in a Known, Predefined State
  • Offered in QFN-32 Package
  • ESD Protection Exceeds 2000 V HBM
  • Industrial Temperature Range: –40°C to +85°C
  • APPLICATIONS
    • Data Converter and Data Aggregation Clocking
    • Wireless Infrastructure
    • Switches and Routers
    • Medical Electronics
    • Military and Aerospace
    • Industrial
    • Clock Generation and Jitter Cleaning


All other trademarks are the property of their respective owners

  • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter
  • Fully Configurable Outputs Including Frequency and Output Format
  • Smart Input Multiplexer Automatically Switches Between One of Two Reference Inputs
  • Multiple Operational Modes Include Clock Generation Through Crystal, SERDES Start-Up Mode, Jitter Cleaning, and Oscillator Based Holdover Mode
  • Integrated EEPROM Determines Device Configuration at Power Up
  • Excellent Jitter Performance
  • Integrated Frequency Synthesizer Including PLL, Multiple VCOs, and Loop Filter:
    • Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode
    • Programmable Charge Pump Gain and Loop Filter Settings
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz to 2.356 GHz.
  • Universal Output Blocks Support Up to 2 Differential, 4 Single-Ended, or Combinations of Differential or Single-Ended:
    • 0.5 ps RMS (10 kHz to 20 MHz) Output Jitter Performance
    • Low Output Phase Noise: –130 dBc/Hz at 1 MHz Offset, Fc = 491.52 MHz
    • Output Frequency Ranges From 10.94 MHz to 1.175 GHz in Synthesizer Mode
    • LVPECL, LVDS, and LVCMOS
    • Independent Output Dividers Support Divide Ratios for 1, 2, 3, 4, 5, 8, 10, 12, 16, 20, 24, and 32
  • Flexible Inputs With Innovative Smart Multiplexer:
    • Two Universal Differential Inputs Accept Frequencies from 1 MHz up to 500 MHz (LVPECL), 500 MHz (LVDS), or 250 MHz (LVCMOS)
    • One Auxiliary Input Accepts Crystals in the Range of 2 MHz to 42 MHz
    • Clock Generator Mode Using Crystal Input
    • Smart Input Multiplexer Can be Configured to Automatically Switch Between Highest Priority Clock Source Available Allowing for Fail-Safe Operation
  • Typical Power Consumption 750 mW at 3.3 V
  • Integrated EEPROM Stores Default Settings; Therefore, the Device Can Power Up in a Known, Predefined State
  • Offered in QFN-32 Package
  • ESD Protection Exceeds 2000 V HBM
  • Industrial Temperature Range: –40°C to +85°C
  • APPLICATIONS
    • Data Converter and Data Aggregation Clocking
    • Wireless Infrastructure
    • Switches and Routers
    • Medical Electronics
    • Military and Aerospace
    • Industrial
    • Clock Generation and Jitter Cleaning


All other trademarks are the property of their respective owners

The CDCE62002 device is a high-performance clock generator featuring low output jitter, a high degree of configurability through a SPI interface, and programmable start-up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5 ps RMS(1).

It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes two individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 10.94 MHz to 1.175 GHz(2)). If Both outputs are configured in single-ended mode (such as LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential inputs which support frequencies up to 500 MHz and an auxiliary input that can be configured to connect to an external AT-Cut crystal through an onboard oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference through the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.

(1) 10-kHz to 20-MHz integration bandwidth.
(2) Frequency range depends on operational mode and output format selected.

The CDCE62002 device is a high-performance clock generator featuring low output jitter, a high degree of configurability through a SPI interface, and programmable start-up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5 ps RMS(1).

It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes two individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 10.94 MHz to 1.175 GHz(2)). If Both outputs are configured in single-ended mode (such as LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential inputs which support frequencies up to 500 MHz and an auxiliary input that can be configured to connect to an external AT-Cut crystal through an onboard oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference through the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.

(1) 10-kHz to 20-MHz integration bandwidth.
(2) Frequency range depends on operational mode and output format selected.

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类型 标题 下载最新的英语版本 日期
* 数据表 CDCE62002 Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs 数据表 (Rev. E) PDF | HTML 2016年 10月 9日
设计指南 适用于 Xilinx FPGA 的模拟器件 解决方案指南 2012年 4月 24日
用户指南 Two/Four Output Low Noise Clock Evaluation Board 2009年 6月 19日

设计和开发

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评估板

CDCE62002EVM — CDCE62002 评估模块

CDCE62002EVM 是用于 CDCE62002 的评估模块。CDCE62002 是高性能时钟发生器,它具有低输出抖动、高度可配置性(通过 SPI 接口进行配置)和由片上 EEPROM 确定的可编程启动模式。CDCE62002 实现了低于 0.5ps RMS 的抖动性能。

用户指南: PDF
TI.com 上无现货
评估模块 (EVM) 用 GUI

SCAC112 CDCE62002EVM GUI

支持的产品和硬件

支持的产品和硬件

产品
时钟发生器
CDCE62002 具有集成双通道 VCO 的 4 路输出时钟发生器/抖动消除器
硬件开发
评估板
CDCE62002EVM CDCE62002 评估模块
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仿真模型

CDCE62002 IBIS Model

SCAM063.ZIP (68 KB) - IBIS Model
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VQFN (RHB) 32 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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