The \x92FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE\) input is low. The register is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop output (O). CE\ must be stable only one setup time prior to the low-to-high clock transition for predictable operation.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | 8-Bit Registers datasheet (Rev. A) | 01 Oct 2001 | |
| * | SMD | CY54FCT377T SMD 5962-92219 | 21 Jun 2016 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 Dec 2022 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 22 Jun 2004 | ||
| User guide | CYFCT Parameter Measurement Information | 02 Apr 2001 | ||
| Selection guide | Advanced Bus Interface Logic Selection Guide | 09 Jan 2001 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | Download |
|---|---|---|
| LCCC (FK) | 20 | View options |
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.