DLPS026E August 2012  – May 2017 DLP7000


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Storage Conditions
    3. 7.3 ESD Ratings
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 LVDS Timing Requirements
    8. 7.8 LVDS Waveform Requirements
    9. 7.9 Serial Control Bus Timing Requirements
    10. 7.10Systems Mounting Interface Loads
    11. 7.11Micromirror Array Physical Characteristics
    12. 7.12Micromirror Array Optical Characteristics
    13. 7.13Window Characteristics
    14. 7.14Chipset Component Usage Specification
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1DLPC410 Chipset DMD Features
        1. - Digital Controller for DLP Discovery 4100 Chipset
        2. - DMD Micromirror Driver
        3. - PROM for DLP Discovery 4100 Chipset
        4. - DLP 0.7 XGA 2xLVDS Type-A DMD
          1. XGA Chip Set Interfaces
            1. Interface Description
              1. IO
              3. Device Detection
              4. Down
          2. to DMD Interface
            1. to DMD IO Description
            2. Flow
          3. to DLPA200 Interface
            1. Operation
            2. to DLPA200 IO Description
          4. to DLP7000 Interface
            1. to DLP7000 Interface Overview
        5. Conditions
    4. 8.4Device Functional Modes
      1. 8.4.1DMD Operation
        1. Block Mode
        2. Block Mode
        3. Block Mode
        4. Mode
    5. 8.5Window Characteristics and Optics
      1. 8.5.1Optical Interface and System Image Quality
      2. 8.5.2Numerical Aperture and Stray Light Control
      3. 8.5.3Pupil Match
      4. 8.5.4Illumination Overfill
    6. 8.6Micromirror Array Temperature Calculation
      1. 8.6.1Package Thermal Resistance
      2. 8.6.2Case Temperature
      3. 8.6.3Micromirror Array Temperature Calculation
    7. 8.7Micromirror Landed-On/Landed-Off Duty Cycle
      1. 8.7.1Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Device Description
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1Layout Guidelines
      1. 11.1.1Impedance Requirements
      2. 11.1.2PCB Signal Routing
      3. 11.1.3Fiducials
      4. 11.1.4DMD Interface
        1. Length Matching
      5. 11.1.5DLP7000 Decoupling
        1. Capacitors
      6. 11.1.6VCC and VCC2
      7. 11.1.7DMD Layout
      8. 11.1.8DLPA200
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Device Support
      1. 12.1.1Device Nomenclature
      2. 12.1.2Device Marking
    2. 12.2Documentation Support
      1. 12.2.1Related Documents
    3. 12.3Related Links
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information


  • 0.7-Inch Diagonal Micromirror Array
    • 1024 × 768 Array of Aluminum, Micrometer-Sized Mirrors
    • 13.68-µm Micromirror Pitch
    • ±12° Micromirror Tilt Angle (Relative to Flat State)
    • Designed for Corner Illumination
  • Designed for Use with Broadband Visible Light (400 to 700 nm):
    • Window Transmission 97% (Single Pass, Through Two Window Surfaces)
    • Micromirror Reflectivity 88%
    • Array Diffraction Efficiency 86%
    • Array Fill Factor 92%
  • Two 16-Bit, Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) Input Data Buses
  • Up to 400 MHz Input Data Clock Rate
  • 40.64-mm by 31.75-mm by 6.0-mm Package Footprint
  • Hermetic Package


  • Industrial
    • Digital Imaging Lithography
    • Laser Marking
    • LCD and OLED Repair
    • Computer-to-Plate Printers
    • SLA 3D Printers
    • 3D Scanners for Machine Vision and Factory Automation
    • Flat Panel Lithography
  • Medical
    • Phototherapy Devices
    • Ophthalmology
    • Direct Manufacturing
    • Hyperspectral Imaging
    • 3D Biometrics
    • Confocal Microscopes
  • Display
    • 3D Imaging Microscopes
    • Adaptive Illumination
    • Augmented Reality and Information Overlay


The DLP7000 XGA Chipset is part of the DLP® Discovery™ 4100 platform, which enables high resolution and high performance spatial light modulation. The DLP7000 is the digital micromirror device (DMD) fundamental to the 0.7 XGA chipset, and currently supports the fastest pattern rates in the DLP catalog portfolio. The DLP Discovery 4100 platform also provides the highest level of individual micromirror control with the option for random row addressing. Combined with a hermetic package, the unique capability and value offered by DLP7000 makes it well suited to support a wide variety of industrial, medical, and advanced display applications.

In addition to the DLP7000 DMD, the 0.7 XGA Chipset includes these components:

  • Dedicated DLPC410 controller for high speed pattern rates of >32000 Hz (1-bit binary) and >1900 Hz (8-bit gray)
  • One unit DLPR410 (DLP Discovery 4100 Configuration PROM)
  • One unit DLPA200 (DMD Micromirror Driver)

Device Information(1)

DLP7000LCCC (203)40.64 mm × 31.75 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.
  2. Simplified Schematic

    DLP7000 Simplified_Diagram_small_DLP7000_update.gif

Revision History

Changes from D Revision (November 2015) to E Revision

  • Clarified TGRADIENT footnoteGo
  • Changed Tstg to TDMDGo
  • Changed Environmental sections of Recommended Operating Conditions table - Simplified to one Environmental section with Illumination power densities in a single group Go
  • Changed 400 to 420 nm illumination power density max from 2.5 to 11 W/cm2 and added 16.2 W max optical power in Recommended Operating Conditions Go
  • Collapsed Operating case temperature points 1 & 2 with point 3 & array to one entry - identical specifications in Recommended Operating ConditionsGo
  • Changed TC2 to TP1 to follow latest thermal test point nomenclature convention in Thermal InformationGo
  • Changed Micromirror active border from 10 to correct value of 6 Go
  • Changed micromirror crossover to mean transition time and renamed previous crossover to micromirror switching time typical micromirror crossover time typo (16 µs to 13 µs)Go
  • Added typical micromirror switching time - 13 µsGo
  • Changed "Micromirror switching time" to "Array switching time" for clarity Go
  • Added clarification to Micromirror switching time at 400 MHz with global reset Go
  • Changed references to D4100 Discovery to DPC410 Go
  • Changed Thermal Test Point Location drawing to current numbering convention Go
  • Updated Figure 22Go
  • Removed link to DLP Discovery 4100 chipset datasheetGo
  • Added DLPR410 to Related Links tableGo

Changes from C Revision (April 2014) to D Revision

Changes from B Revision (June 2013) to C Revision

  • Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Deleted / DLPR4101 Enhanced PROM from Chipset ListGo
  • Corrected VCC2 max to 8 V Go
  • Added array temperature vs duty cycle graphGo
  • Replaced serial communications bus timing parametersGo
  • Converted interface loads to NewtonsGo
  • Grayed out LVDS buses that are unused on DLP7000Go
  • Added micromirror landed duty cycle sectionGo
  • Changed to DLP7000Go
  • Deleted / DLPR4101 Enhanced PROM from Related DocumentationGo

Changes from A Revision (September 2012) to B Revision

  • Added / DLPR4101 Enhanced PROM to DLPR410 in Chipset ListGo
  • Changed pin number of DCLK_AN From: D19 To: B22 Go
  • Changed pin number of DCLK_AP From: E19 To: B24 Go
  • Changed pin number of DCLK_BN From: M19 To: AB22 Go
  • Changed pin number of DCLK_BP From: N19 To: AB24 Go
  • Added / DLPR4101 Enhanced PROM to DLPR410 in Related DocumentationGo

Changes from * Revision (August 2012) to A Revision

  • Changed the device from 'Product Preview' to 'Production'Go