Digital Controller for Discovery 4100 chipset - DLPC410

DLPC410 (ACTIVE)

Digital Controller for Discovery 4100 chipset

Description

The DLPC410 offers the highest speed pattern rates in the DLP Advanced Light Control portfolio with the option for random row addressing. The DLPC410 is a digital controller that supports both the 0.7 XGA chipset and 0.95 1080p chipset. DLPC410 provides reliable operation of two groups of digital micromirror device (DMD) options, DLP7000 / DLP7000UV and DLP9500 / DLP9500UV; reliable operation of the DLPA200 DMD Micromirror Driver; and a convenient, multi-functional interface between user electronics and the DMD.

The DLPC410 provides a high-speed data and control interface for the DLP7000 / DLP7000UV DMD and DLP9500 / DLP9500UV DMD enabling binary pattern rates of up to 32 kHz and 23 kHz, respectively. These fast pattern rates set DLP technology apart from other spatial light modulators and offer customers a strategic advantage for equipment needing fast, accurate, and programmable light steering capability. Moreover, the DLPC410 provides the DMD mirror clocking pulse and timing information to the DLPA200 DMD Micromirror Driver. The unique capability and value offered by DLPC410 makes it well suited to support a wide variety of industrial, medical, and advanced display applications.

In DLP-based electronics solutions, image data is 100% digital from the DLPC410 input port to the projected image. The image stays in digital form and is never converted into an analog signal. The DLPC410 processes the digital input image and converts the data into a format needed by the image on the DMD. The DMD then steers the light using binary pulse-width modulation (PWM) for each pixel mirror.

Features

  • Operates the Following DLP® Chipset
    Components:
    • DMD: DLP7000 / DLP7000UV and DLP9500 /
      DLP9500UV
    • DMD Micromirror Driver: DLPA200
    • PROM: DLPR410
  • Enables Highest Speed DMD Pattern Rates
    • 1-Bit Binary Pattern Rates up to 32 kHz
    • 8-Bit Monochrome Pattern Rates up to 1.9 kHz
  • Allows Input Clock Rates Between 200 MHz and
    400 MHz
  • Provides up to a 64-Bit LVDS Data Bus Interface
  • Supports Random DMD Row Addressing
  • Compatible With a Variety of User Defined
    Processors or FPGAs
  • 676-Pin, 27-mm × 27-mm PBGA Package

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Parametrics Compare all products in Pattern Rate (>=8 kHz)

 
Component Type
Max Display Resolution
Max Pattern Rate, Binary (Hz)
# Triggers (Input / Output)
GPIO
Package Group
Chipset Family
Micromirror Driver Support
DLPC410 DLPC910
Digital Controller     Digital Controller    
1080p     WQXGA    
32,552     14989    
0 / 1     0 / 0    
0     0    
FCBGA     FCBGA    
DLP7000
DLP9500    
DLP9000    
External     Integrated    

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