SPRS950C December 2015  – June 2017 DRA744 , DRA745 , DRA746 , DRA750 , DRA756

PRODUCTION DATA. 

  1. Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3 Description
    4. 1.4Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1Device Comparison Table
    2. 3.2Related Products
  4. Terminal Configuration and Functions
    1. 4.1Terminal Assignment
      1. 4.1.1Unused Balls Connection Requirements
    2. 4.2Ball Characteristics
    3. 4.3Multiplexing Characteristics
    4. 4.4Signal Descriptions
      1. 4.4.1 Video Input Ports (VIP)
      2. 4.4.2 Display Subsystem - Video Output Ports
      3. 4.4.3 Display Subsystem - High-Definition Multimedia Interface (HDMI)
      4. 4.4.4 External Memory Interface (EMIF)
      5. 4.4.5 General-Purpose Memory Controller (GPMC)
      6. 4.4.6 Timers
      7. 4.4.7 Inter-Integrated Circuit Interface (I2C)
      8. 4.4.8 HDQ / 1-Wire Interface (HDQ1W)
      9. 4.4.9 Universal Asynchronous Receiver Transmitter (UART)
      10. 4.4.10Multichannel Serial Peripheral Interface (McSPI)
      11. 4.4.11Quad Serial Peripheral Interface (QSPI)
      12. 4.4.12Multichannel Audio Serial Port (McASP)
      13. 4.4.13Universal Serial Bus (USB)
      14. 4.4.14SATA
      15. 4.4.15Peripheral Component Interconnect Express (PCIe)
      16. 4.4.16Controller Area Network Interface (DCAN)
      17. 4.4.17Ethernet Interface (GMAC_SW)
      18. 4.4.18Media Local Bus (MLB) Interface
      19. 4.4.19eMMC/SD/SDIO
      20. 4.4.20General-Purpose Interface (GPIO)
      21. 4.4.21Keyboard controller (KBD)
      22. 4.4.22Pulse Width Modulation (PWM) Interface
      23. 4.4.23Audio Tracking Logic (ATL)
      24. 4.4.24Test Interfaces
      25. 4.4.25System and Miscellaneous
        1. 4.4.25.1Sysboot
        2. 4.4.25.2Power, Reset, and Clock Management (PRCM)
        3. 4.4.25.3Real Time Clock (RTC) Interface
        4. 4.4.25.4System Direct Memory Access (SDMA)
        5. 4.4.25.5Interrupt Controllers (INTC)
        6. 4.4.25.6Observability
      26. 4.4.26Power Supplies
  5. Specifications
    1. 5.1Absolute Maximum Ratings
    2. 5.2ESD Ratings
    3. 5.3Power on Hour (POH) Limits
    4. 5.4Recommended Operating Conditions
    5. 5.5Operating Performance Points
      1. 5.5.1AVS and ABB Requirements
      2. 5.5.2Voltage And Core Clock Specifications
      3. 5.5.3Maximum Supported Frequency
    6. 5.6Power Consumption Summary
    7. 5.7Electrical Characteristics
      1. 5.7.1 LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2 HDMIPHY DC Electrical Characteristics
      3. 5.7.3 Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4 IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5 IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6 LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7 ILVDS18 Buffers DC Electrical Characteristics
      8. 5.7.8 BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9 BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13SATAPHY DC Electrical Characteristics
      14. 5.7.14PCIEPHY DC Electrical Characteristics
    8. 5.8Thermal Resistance Characteristics
      1. 5.8.1Package Thermal Characteristics
    9. 5.9Power Supply Sequences
  6. Clock Specifications
    1. 6.1Input Clock Specifications
      1. 6.1.1Input Clock Requirements
      2. 6.1.2System Oscillator OSC0 Input Clock
        1. 6.1.2.1OSC0 External Crystal
        2. 6.1.2.2OSC0 Input Clock
      3. 6.1.3Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1OSC1 External Crystal
        2. 6.1.3.2OSC1 Input Clock
      4. 6.1.4RTC Oscillator Input Clock
        1. 6.1.4.1RTC Oscillator External Crystal
        2. 6.1.4.2RTC Oscillator Input Clock
    2. 6.2RC On-die Oscillator Clock
    3. 6.3DPLLs, DLLs Specifications
      1. 6.3.1DPLL Characteristics
      2. 6.3.2DLL Characteristics
      3. 6.3.3DPLL and DLL Noise Isolation
  7. Timing Requirements and Switching Characteristics
    1. 7.1 Timing Test Conditions
    2. 7.2 Interface Clock Specifications
      1. 7.2.1Interface Clock Terminology
      2. 7.2.2Interface Clock Frequency
    3. 7.3 Timing Parameters and Information
      1. 7.3.1Parameter Information
        1. 7.3.1.11.8V and 3.3V Signal Transition Levels
        2. 7.3.1.21.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3Timing Parameters and Board Routing Analysis
    4. 7.4 Recommended Clock and Control Signal Transition Behavior
    5. 7.5 Virtual and Manual I/O Timing Modes
    6. 7.6 Video Input Ports (VIP)
    7. 7.7  Display Subsystem - Video Output Ports
    8. 7.8 Display Subsystem - High-Definition Multimedia Interface (HDMI)
    9. 7.9 External Memory Interface (EMIF)
    10. 7.10General-Purpose Memory Controller (GPMC)
      1. 7.10.1GPMC/NOR Flash Interface Synchronous Timing
      2. 7.10.2GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.10.3GPMC/NAND Flash Interface Asynchronous Timing
    11. 7.11Timers
    12. 7.12Inter-Integrated Circuit Interface (I2C)
    13. 7.13HDQ / 1-Wire Interface (HDQ1W)
      1. 7.13.1HDQ / 1-Wire — HDQ Mode
      2. 7.13.2HDQ/1-Wire—1-Wire Mode
    14. 7.14Universal Asynchronous Receiver Transmitter (UART)
    15. 7.15Multichannel Serial Peripheral Interface (McSPI)
    16. 7.16Quad Serial Peripheral Interface (QSPI)
    17. 7.17Multichannel Audio Serial Port (McASP)
    18. 7.18Universal Serial Bus (USB)
      1. 7.18.1USB1 DRD PHY
      2. 7.18.2USB2 PHY
      3. 7.18.3USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
    19. 7.19Serial Advanced Technology Attachment (SATA)
    20. 7.20Peripheral Component Interconnect Express (PCIe)
    21. 7.21Controller Area Network Interface (DCAN)
    22. 7.22Ethernet Interface (GMAC_SW)
      1. 7.22.1GMAC MII Timings
      2. 7.22.2GMAC MDIO Interface Timings
      3. 7.22.3GMAC RMII Timings
      4. 7.22.4GMAC RGMII Timings
    23. 7.23Media Local Bus (MLB) interface
    24. 7.24eMMC/SD/SDIO
      1. 7.24.1MMC1—SD Card Interface
        1. 7.24.1.1Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3SDR12, 4-bit data, half-cycle
        4. 7.24.1.4SDR25, 4-bit data, half-cycle
        5. 7.24.1.5UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7UHS-I DDR50, 4-bit data
      2. 7.24.2MMC2 — eMMC
        1. 7.24.2.1Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3High-speed HS200 JC64 SDR, 8-bit data, half cycle
        4. 7.24.2.4High-speed JC64 DDR, 8-bit data
      3. 7.24.3MMC3 and MMC4—SDIO/SD
        1. 7.24.3.1MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2MMC3 and MMC4, SD High Speed
        3. 7.24.3.3MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25General-Purpose Interface (GPIO)
    26. 7.26Audio Tracking Logic (ATL)
      1. 7.26.1ATL Electrical Data/Timing
    27. 7.27System and Miscellaneous interfaces
    28. 7.28Test Interfaces
      1. 7.28.1IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1JTAG Electrical Data/Timing
      2. 7.28.2Trace Port Interface Unit (TPIU)
        1. 7.28.2.1TPIU PLL DDR Mode
  8. Applications, Implementation, and Layout
    1. 8.1Introduction
      1. 8.1.1Initial Requirements and Guidelines
    2. 8.2Power Optimizations
      1. 8.2.1Step 1: PCB Stack-up
      2. 8.2.2Step 2: Physical Placement
      3. 8.2.3Step 3: Static Analysis
        1. 8.2.3.1PDN Resistance and IR Drop
      4. 8.2.4Step 4: Frequency Analysis
      5. 8.2.5System ESD Generic Guidelines
        1. 8.2.5.1System ESD Generic PCB Guideline
        2. 8.2.5.2Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 8.2.6EMI / EMC Issues Prevention
        1. 8.2.6.1Signal Bandwidth
        2. 8.2.6.2Signal Routing
          1. 8.2.6.2.1Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2Signal Routing—Outer Layer Routing
        3. 8.2.6.3Ground Guidelines
          1. 8.2.6.3.1PCB Outer Layers
          2. 8.2.6.3.2Metallic Frames
          3. 8.2.6.3.3Connectors
          4. 8.2.6.3.4Guard Ring on PCB Edges
          5. 8.2.6.3.5Analog and Digital Ground
    3. 8.3Core Power Domains
      1. 8.3.1General Constraints and Theory
      2. 8.3.2Voltage Decoupling
      3. 8.3.3Static PDN Analysis
      4. 8.3.4Dynamic PDN Analysis
      5. 8.3.5Power Supply Mapping
      6. 8.3.6DPLL Voltage Requirement
      7. 8.3.7Example PCB Design
        1. 8.3.7.1Example Stack-up
        2. 8.3.7.2vdd_mpu Example Analysis
    4. 8.4Single-Ended Interfaces
      1. 8.4.1General Routing Guidelines
      2. 8.4.2QSPI Board Design and Layout Guidelines
    5. 8.5Differential Interfaces
      1. 8.5.1General Routing Guidelines
      2. 8.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 8.5.2.1Background
        2. 8.5.2.2USB PHY Layout Guide
          1. 8.5.2.2.1General Routing and Placement
          2. 8.5.2.2.2Specific Guidelines for USB PHY Layout
            1. 8.5.2.2.2.1 Analog, PLL, and Digital Power Supply Filtering
            2. 8.5.2.2.2.2 Analog, Digital, and PLL Partitioning
            3. 8.5.2.2.2.3 Board Stackup
            4. 8.5.2.2.2.4 Cable Connector Socket
            5. 8.5.2.2.2.5 Clock Routings
            6. 8.5.2.2.2.6 Crystals/Oscillator
            7. 8.5.2.2.2.7 DP/DM Trace
            8. 8.5.2.2.2.8 DP/DM Vias
            9. 8.5.2.2.2.9 Image Planes
            10. 8.5.2.2.2.10JTAG Interface
            11. 8.5.2.2.2.11Power Regulators
        3. 8.5.2.3Electrostatic Discharge (ESD)
          1. 8.5.2.3.1IEC ESD Stressing Test
            1. 8.5.2.3.1.1Test Mode
            2. 8.5.2.3.1.2Air Discharge Mode
            3. 8.5.2.3.1.3Test Type
          2. 8.5.2.3.2TI Component Level IEC ESD Test
          3. 8.5.2.3.3Construction of a Custom USB Connector
          4. 8.5.2.3.4ESD Protection System Design Consideration
        4. 8.5.2.4References
      3. 8.5.3USB 3.0 Board Design and Layout Guidelines
        1. 8.5.3.1USB 3.0 interface introduction
        2. 8.5.3.2USB 3.0 General routing rules
      4. 8.5.4HDMI Board Design and Layout Guidelines
        1. 8.5.4.1HDMI Interface Schematic
        2. 8.5.4.2TMDS General Routing Guidelines
        3. 8.5.4.3TPD5S115
        4. 8.5.4.4HDMI ESD Protection Device (Required)
        5. 8.5.4.5PCB Stackup Specifications
        6. 8.5.4.6Grounding
      5. 8.5.5SATA Board Design and Layout Guidelines
        1. 8.5.5.1SATA Interface Schematic
        2. 8.5.5.2Compatible SATA Components and Modes
        3. 8.5.5.3PCB Stackup Specifications
        4. 8.5.5.4Routing Specifications
      6. 8.5.6PCIe Board Design and Layout Guidelines
        1. 8.5.6.1PCIe Connections and Interface Compliance
          1. 8.5.6.1.1Coupling Capacitors
          2. 8.5.6.1.2Polarity Inversion
        2. 8.5.6.2Non-standard PCIe connections
          1. 8.5.6.2.1PCB Stackup Specifications
          2. 8.5.6.2.2Routing Specifications
            1. 8.5.6.2.2.1Impedance
            2. 8.5.6.2.2.2Differential Coupling
            3. 8.5.6.2.2.3Pair Length Matching
        3. 8.5.6.3LJCB_REFN/P Connections
    6. 8.6Clock Routing Guidelines
      1. 8.6.132-kHz Oscillator Routing
      2. 8.6.2Oscillator Ground Connection
    7. 8.7DDR2/DDR3 Board Design and Layout Guidelines
      1. 8.7.1DDR2/DDR3 General Board Layout Guidelines
      2. 8.7.2DDR2 Board Design and Layout Guidelines
        1. 8.7.2.1Board Designs
        2. 8.7.2.2DDR2 Interface
          1. 8.7.2.2.1 DDR2 Interface Schematic
          2. 8.7.2.2.2 Compatible JEDEC DDR2 Devices
          3. 8.7.2.2.3 PCB Stackup
          4. 8.7.2.2.4 Placement
          5. 8.7.2.2.5 DDR2 Keepout Region
          6. 8.7.2.2.6 Bulk Bypass Capacitors
          7. 8.7.2.2.7 High-Speed Bypass Capacitors
          8. 8.7.2.2.8 Net Classes
          9. 8.7.2.2.9 DDR2 Signal Termination
          10. 8.7.2.2.10VREF Routing
        3. 8.7.2.3DDR2 CK and ADDR_CTRL Routing
      3. 8.7.3DDR3 Board Design and Layout Guidelines
        1. 8.7.3.1 Board Designs
          1. 8.7.3.1.1DDR3 versus DDR2
        2. 8.7.3.2 DDR3 EMIFs
        3. 8.7.3.3 DDR3 Device Combinations
        4. 8.7.3.4 DDR3 Interface Schematic
          1. 8.7.3.4.132-Bit DDR3 Interface
          2. 8.7.3.4.216-Bit DDR3 Interface
        5. 8.7.3.5 Compatible JEDEC DDR3 Devices
        6. 8.7.3.6 PCB Stackup
        7. 8.7.3.7 Placement
        8. 8.7.3.8 DDR3 Keepout Region
        9. 8.7.3.9 Bulk Bypass Capacitors
        10. 8.7.3.10High-Speed Bypass Capacitors
          1. 8.7.3.10.1Return Current Bypass Capacitors
        11. 8.7.3.11Net Classes
        12. 8.7.3.12DDR3 Signal Termination
        13. 8.7.3.13VREF_DDR Routing
        14. 8.7.3.14VTT
        15. 8.7.3.15CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.7.3.15.1Four DDR3 Devices
            1. 8.7.3.15.1.1CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.7.3.15.1.2CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.7.3.15.2Two DDR3 Devices
            1. 8.7.3.15.2.1CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.7.3.15.2.2CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.7.3.15.3One DDR3 Device
            1. 8.7.3.15.3.1CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.7.3.15.3.2CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.7.3.16Data Topologies and Routing Definition
          1. 8.7.3.16.1DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.7.3.16.2DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.7.3.17Routing Specification
          1. 8.7.3.17.1CK and ADDR_CTRL Routing Specification
          2. 8.7.3.17.2DQS and DQ Routing Specification
  9. Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1Standard Package Symbolization
      2. 9.1.2Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
      1. 9.3.1FCC Warning
      2. 9.3.2Information About Cautions and Warnings
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Related Links
    6. 9.6 Community Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Export Control Notice
    10. 9.10Glossary
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1Mechanical Data

Device Overview

Features

  • Architecture Designed for Infotainment Applications
  • Video, Image, and Graphics Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
  • Dual ARM® Cortex®-A15 Microprocessor Subsystem
  • Up to two C66x™ Floating-Point VLIW DSP
    • Fully Object-Code Compatible With C67x and C64x+™
    • Up to Thirty-two 16 x 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 2.5MB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB Supported per EMIF
  • Dual ARM® Cortex®-M4 Image Processing Units (IPU)
  • Up to Two Embedded Vision Engines (EVEs)
  • IVA Subsystem
  • Display Subsystem
    • Display Controller With DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • Video Processing Engine (VPE)
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante™ GC320 Core
  • Dual-Core PowerVR® SGX544™ 3D GPU
  • Three Video Input Port (VIP) Modules
    • Support for up to 10 Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Five Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • SATA Interface
  • Media Local Bus (MLB) Subsystem
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • Three High-Speed USB 2.0 Dual-Role Devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC/SD/SDIO)
  • PCI-Express® 3.0 Subsystems With Two 5-Gbps Lanes
    • One 2-lane Gen2-Compliant Port
    • or Two 1-lane Gen2-Compliant Ports
  • Dual Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • Up to 247 General-Purpose I/O (GPIO) Pins
  • Real-Time Clock Subsystem (RTCSS)
  • Device security features
    • Hardware Crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management
  • On-Chip Debug With CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)

Applications

  • Human-Machine Interface (HMI)
  • Navigation
  • Digital and Analog Radio
  • Rear Seat Entertainment
  • Multimedia Playback
  • Web Browsing
  • ADAS Integration

Description

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core ARM Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The ARM allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the ARM, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.

Device Information

PART NUMBERPACKAGEBODY SIZE
DRA74xFCBGA (760)23.0 mm × 23.0 mm
DRA75xFCBGA (760)23.0 mm × 23.0 mm

Functional Block Diagram

Figure 1-1 is functional block diagram for the device.

DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756 func_sprs857-001.gif Figure 1-1 DRA75x, DRA74x Block Diagram
  1. ECC is only available on EMIF1.