Refer to the PDF data sheet for device specific package drawings
DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.
The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.
Programmability is provided by dual-core ARM Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The ARM allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the ARM, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.
The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.
|PART NUMBER||PACKAGE||BODY SIZE|
|DRA74x||FCBGA (760)||23.0 mm × 23.0 mm|
|DRA75x||FCBGA (760)||23.0 mm × 23.0 mm|
Figure 1-1 is functional block diagram for the device.