Home Interface High-speed SerDes FPD-Link SerDes

DS90C189-Q1

ACTIVE

Low Power 1.8-V Dual Pixel FPD-Link (LVDS) Serializer

Product details

Function Serializer Color depth (bps) 24 Input compatibility LVCMOS Output compatibility LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Automotive Operating temperature range (°C) -40 to 115
Function Serializer Color depth (bps) 24 Input compatibility LVCMOS Output compatibility LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Automotive Operating temperature range (°C) -40 to 115
VQFNP (RTD) 64 81 mm² 9 x 9
  • AEC-Q100 Qualified for Automotive Applications with the Following Specifications:
    • Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature
    • Device HBM ESD Classification Level ±8 kV
    • Device CDM ESD Classification Level ±750 V
  • 150 mW Typical Power Consumption at 185 MHz (SIDO Mode)
  • Drives QXGA and WQXGA Class Displays
  • Two Operating Modes:
    • Single Pixel In, Single Pixel Out (SISO): 105 MHz Maximum
    • Single Pixel In, Dual Pixel Out (SIDO): 185 MHz Maximum
  • Supports 24-Bit RGB
  • Supports 3D+C, 4D+C, 6D+C, 6D+2C, 8D+C, and 8D+2C LVDS Configurations
  • Compatible With FPD-Link Devices
  • Operates Off a Single 1.8-V Supply
  • Interfaces Directly With 1.8-V LVCMOS
  • Less Than 10 mW Power Consumption in Sleep Mode
  • Spread Spectrum Clock Compatible
  • Small 9 mm × 9 mm × 0.9 mm 64-Pin VQFN Package
  • AEC-Q100 Qualified for Automotive Applications with the Following Specifications:
    • Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature
    • Device HBM ESD Classification Level ±8 kV
    • Device CDM ESD Classification Level ±750 V
  • 150 mW Typical Power Consumption at 185 MHz (SIDO Mode)
  • Drives QXGA and WQXGA Class Displays
  • Two Operating Modes:
    • Single Pixel In, Single Pixel Out (SISO): 105 MHz Maximum
    • Single Pixel In, Dual Pixel Out (SIDO): 185 MHz Maximum
  • Supports 24-Bit RGB
  • Supports 3D+C, 4D+C, 6D+C, 6D+2C, 8D+C, and 8D+2C LVDS Configurations
  • Compatible With FPD-Link Devices
  • Operates Off a Single 1.8-V Supply
  • Interfaces Directly With 1.8-V LVCMOS
  • Less Than 10 mW Power Consumption in Sleep Mode
  • Spread Spectrum Clock Compatible
  • Small 9 mm × 9 mm × 0.9 mm 64-Pin VQFN Package

The DS90C189-Q1 is a low power bridge for automotive applications that reduces the size of the RGB interface between the host GPU and the Display.

The DS90C189-Q1Bridge is designed to support single pixel data transmission between a Host and a Flat Panel Display at resolutions of up to QXGA (2048x1536) at 60 Hz. The transmitter converts up to 24 bits (Single Pixel 24-bit color) of 1.8-V LVCMOS data into two channels of 4 data + clock (4D+C) reduced width interface LVDS compatible data streams.

DS90C189-Q1 supports 2 modes of operation.

  • In single pixel mode in/out mode, the device can drive up to SXGA+ (1400x1050) at 60 Hz. In this mode, the device converts one bank of 24-bit RGB data to a one channel 4D+C LVDS data stream.
  • In single pixel in / dual pixel out mode, the device can drive up to WUXGA+ (1920x1440) at 60 Hz. In this configuration, the device provides single-to-dual pixel conversion and converts one bank of 24-bit RGB data into two channels of 4D+C LVDS streams at half the pixel clock rate.

For all the modes, the device supports 24bpp color.

The DS90C189-Q1 is offered in a small 64 pin QFN package and features single 1.8 V supply for minimal power dissipation.

The DS90C189-Q1 is a low power bridge for automotive applications that reduces the size of the RGB interface between the host GPU and the Display.

The DS90C189-Q1Bridge is designed to support single pixel data transmission between a Host and a Flat Panel Display at resolutions of up to QXGA (2048x1536) at 60 Hz. The transmitter converts up to 24 bits (Single Pixel 24-bit color) of 1.8-V LVCMOS data into two channels of 4 data + clock (4D+C) reduced width interface LVDS compatible data streams.

DS90C189-Q1 supports 2 modes of operation.

  • In single pixel mode in/out mode, the device can drive up to SXGA+ (1400x1050) at 60 Hz. In this mode, the device converts one bank of 24-bit RGB data to a one channel 4D+C LVDS data stream.
  • In single pixel in / dual pixel out mode, the device can drive up to WUXGA+ (1920x1440) at 60 Hz. In this configuration, the device provides single-to-dual pixel conversion and converts one bank of 24-bit RGB data into two channels of 4D+C LVDS streams at half the pixel clock rate.

For all the modes, the device supports 24bpp color.

The DS90C189-Q1 is offered in a small 64 pin QFN package and features single 1.8 V supply for minimal power dissipation.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 4
Type Title Date
* Data sheet DS90C189-Q1 Low Power, 1.8 V RGB-to-Open LDI (LVDS) Bridge datasheet (Rev. B) 01 Sep 2020
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 Nov 2018
Technical article Finding the right pixel clock frequency and throughput for an LVDS display resolut PDF | HTML 26 Sep 2018
EVM User's guide DS90C189-Q1EVM User's Guide 03 May 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

DS90C189-Q1 IBIS Model (Rev. A)

SNLM219A.ZIP (74 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Reference designs

TIDEP-01002 — Cost-optimized digital cluster automotive reference design with Jacinto™ automotive processor

The Jacinto™ automotive processor Digital Cluster Automotive Reference Design (DCARD) is a cost-optimized design for reconfigurable digital cluster systems.  DCARD is a complete and self-contained 6-layer PCB design to enable 60fps digital cluster solutions on 1920x720 resolution (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
VQFNP (RTD) 64 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos