The DS90UB926Q-Q1 deserializer, in conjunction with the DS90UB925Q-Q1 serializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image-sensing applications.
This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and low-speed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UB926Q-Q1 deserializer recovers the RGB data, three video control signals, and four synchronized I2S audio signals. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock.
The DS90UB926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB, video control, and audio data.
An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG) and enhanced progressive turnon (EPTO) features.
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|Color Depth (bpp)|
|Pixel Clock Min (MHz)|
|Pixel Clock (Max) (MHz)|
|Total Throughput (Mbps)|
|Operating Temperature Range (C)|
|Package Size: mm2:W x L (PKG)|
|FPD-Link III LVDS||FPD-Link III LVDS|
I2S Surround Audio
|Adaptive Equalizer||Adaptive Equalizer|
|-40 to 105||-40 to 105|
|60WQFN: 81 mm2: 9 x 9(WQFN)||48WQFN: 49 mm2: 7 x 7(WQFN)|
|Order Now||Order Now|