The DS90UH926Q-Q1 deserializer, in conjunction with the DS90UH925Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and low-speed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UH926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB, video control, and audio data. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock.
An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG) and enhanced progressive turnon (EPTO) features.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.For all available packages, see the orderable addendum at the end of the data sheet.
|Color Depth (bpp)|
|Pixel Clock Min (MHz)|
|Pixel Clock (Max) (MHz)|
|Operating Temperature Range (C)|
|Total Throughput (Mbps)|
|FPD-Link III LVDS|
|-40 to 105|
| GPIO |
| SSCG |
| HDCP |