The GC4016 quad receiver chip contain four identical down-conversion circuits. Each downconvert circuit accepts a real sample rate up to 100 MHz, down converts a selected carrier frequency to zero, decimates the signal rate by a programmable factor ranging from 32 to 16,384 and then resamples the channel to adjust the sample rate up or down by an arbitrary factor. In the real output mode the output sample rate is doubled and the signal is output as a real signal centered at Fout/4. The channels may be combined to produce wider band and/or oversampled outputs or to process complex input data. The chip outputs the down-converted signals in any one of several formats (microprocessor, four serial lines, one TDM serial line, nibble, LINK, or 24 bit parallel port. The chip contains two user programmable output filters per path which can be used to arbitrarily shape the received data\x92s spectrum. These filters can be used as Nyquist receive filters for digital data transmission. The chip also contains a resampling filter to provide additional filtering and to allow the user complete flexibility in the selection of input and output sample rates.
Two downconverter paths can be merged to be used as a single complex input down-conversion circuit. Two paths may also be combined to support wider band output rates or oversampled outputs. Four paths may be combined to support both wider band output and oversampling.
The downconverters are designed to maintain over 115 dB of spur free dynamic range and over 100 dB of out of band rejection. A five stage CIC and 20 bit internal datapaths support this high dynamic range signal processing requirement. Each downconvert circuit accepts 16 bit inputs and produces 24 bit outputs (can be rounded back to 12, 16, or 20 bits). The frequencies and phase offsets of the four sine/cosine sequence generators can be independently specified, as can the decimation and filter parameters of each circuit.
On chip diagnostic circuits are provided to simplify system debug and maintenance.
The chip receives configuration and control information over a microprocessor compatible bus consisting of an 8 bit data I/O port, a 5 bit address port, a chip enable strobe, a read strobe and a write strobe. The chip\x92s control registers (8 bits each) are memory mapped into the 5 bit address space of the control port.
Sections 7.9 through 7.12 describe how to use the chip for GSM, D-AMPS, CDMA and UMTS applications, including control register values and filter coefficients.