Product details

Resolution (Bits) 10 Number of channels 6 Sample rate (Msps) 70 Gain (min) (dB) 0 Gain (max) (dB) 26 Pd (typ) (mW) 1020 Supply voltage (max) (V) 3.3 Operating temperature range (°C) 0 to 70 Output data format LVDS Rating Catalog
Resolution (Bits) 10 Number of channels 6 Sample rate (Msps) 70 Gain (min) (dB) 0 Gain (max) (dB) 26 Pd (typ) (mW) 1020 Supply voltage (max) (V) 3.3 Operating temperature range (°C) 0 to 70 Output data format LVDS Rating Catalog
TQFP (PFC) 80 196 mm² 14 x 14
  • 3.3 V Single Supply Operation
  • CDS or S/H Processing
  • 35 MHz Channel Rate
  • Enhanced ESD Protection on Timing, Control and LVDS Pins
  • Low Power CMOS Design
  • 12 Terminal to 16 Terminal (Selectable) LVDS Serialized Data Output
  • 4–Wire Serial Interface
  • 2 Channel Symmetrical Architecture
  • Independent Gain and Offset Correction for Each Channel
  • Digital Black Level Calibration for Each Channel
  • Digital White Level Calibration for Each Channel
  • Programmable Input Clamp
  • Key Specifications
    • Maximum Input Level:
      • 1.2 Vp–p (CDS Gain = 1.0)
      • 0.58 Vp–p (CDS Gain = 2.1)
    • Input Sample Rate:
      • 5 to 35 MSPS – 6ch mode
      • 10 to 35 MSPS – 3ch mode
    • PGA Gain Range: 1x to 10x (0 to 20 dB)
    • CDS/SH Gain Settings: 1x or 2.1x
    • Total Channel Gain: 1x to 21x (0 to 26 dB)
    • PGA Gain Resolution: 8 bits – Analog
    • ADC Resolution: 10 bits
    • ADC Sampling Rate: 10 to 70 MSPS
    • SNR: 68.5 dB (Gain = 1x)
    • Offset DAC Range:
      • ±111 mV or ±59.5 mV – FDAC
      • ±281 mV – CDAC
    • Offset DAC Resolution:
      • ±10 bits – FDAC
      • ±4 bits – CDAC
    • Supply Voltage: 3.0 V to 3.6 V
    • Power Dissipation: 1.02 W (typical)
  • 3.3 V Single Supply Operation
  • CDS or S/H Processing
  • 35 MHz Channel Rate
  • Enhanced ESD Protection on Timing, Control and LVDS Pins
  • Low Power CMOS Design
  • 12 Terminal to 16 Terminal (Selectable) LVDS Serialized Data Output
  • 4–Wire Serial Interface
  • 2 Channel Symmetrical Architecture
  • Independent Gain and Offset Correction for Each Channel
  • Digital Black Level Calibration for Each Channel
  • Digital White Level Calibration for Each Channel
  • Programmable Input Clamp
  • Key Specifications
    • Maximum Input Level:
      • 1.2 Vp–p (CDS Gain = 1.0)
      • 0.58 Vp–p (CDS Gain = 2.1)
    • Input Sample Rate:
      • 5 to 35 MSPS – 6ch mode
      • 10 to 35 MSPS – 3ch mode
    • PGA Gain Range: 1x to 10x (0 to 20 dB)
    • CDS/SH Gain Settings: 1x or 2.1x
    • Total Channel Gain: 1x to 21x (0 to 26 dB)
    • PGA Gain Resolution: 8 bits – Analog
    • ADC Resolution: 10 bits
    • ADC Sampling Rate: 10 to 70 MSPS
    • SNR: 68.5 dB (Gain = 1x)
    • Offset DAC Range:
      • ±111 mV or ±59.5 mV – FDAC
      • ±281 mV – CDAC
    • Offset DAC Resolution:
      • ±10 bits – FDAC
      • ±4 bits – CDAC
    • Supply Voltage: 3.0 V to 3.6 V
    • Power Dissipation: 1.02 W (typical)

The LM98620 is a fully integrated, 10–Bit, 70 MSPS signal processing solution for high performance digital color copiers, scanners, and other image processing applications. High-speed signal throughput is achieved with an innovative six channel architecture utilizing Correlated Double Sampling (CDS), or Sample and Hold (SH) type sampling. Gain settings of 1x or 2x are available in the CDS/SH input stage. Each channel has a dedicated 1x to 10x (8 bit) PGA that allows accurate gain adjustment. The Digital White Level auto calibration loop can automatically set the PGA value to achieve a selected white target level. Each channel also has a ±4 bit coarse and ±10 bit fine analog offset correction DAC that allows offset correction before the sample-and-hold amplifier. These correction values can be controlled by an automated Digital Black Level correction loop. The PGA and offset DACs for each channel are programmed independently allowing unique values of gain and offset for each of the six channels. A 2-to-1 multiplexing scheme routes the signals to three 70 MHz high performance ADCs. The fully differential processing channels achieve exceptional noise immunity, having a very low noise floor of –68.5dB. The 10 bit analog-to-digital converters have excellent dynamic performance, making the LM98620 transparent in the image reproduction chain.

The LM98620 is a fully integrated, 10–Bit, 70 MSPS signal processing solution for high performance digital color copiers, scanners, and other image processing applications. High-speed signal throughput is achieved with an innovative six channel architecture utilizing Correlated Double Sampling (CDS), or Sample and Hold (SH) type sampling. Gain settings of 1x or 2x are available in the CDS/SH input stage. Each channel has a dedicated 1x to 10x (8 bit) PGA that allows accurate gain adjustment. The Digital White Level auto calibration loop can automatically set the PGA value to achieve a selected white target level. Each channel also has a ±4 bit coarse and ±10 bit fine analog offset correction DAC that allows offset correction before the sample-and-hold amplifier. These correction values can be controlled by an automated Digital Black Level correction loop. The PGA and offset DACs for each channel are programmed independently allowing unique values of gain and offset for each of the six channels. A 2-to-1 multiplexing scheme routes the signals to three 70 MHz high performance ADCs. The fully differential processing channels achieve exceptional noise immunity, having a very low noise floor of –68.5dB. The 10 bit analog-to-digital converters have excellent dynamic performance, making the LM98620 transparent in the image reproduction chain.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet LM98620 10-bit 70 MSPS 6 Channel Imaging Signal Processor with LVDS Output datasheet (Rev. C) 14 May 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

LM98620 IBIS Model

SNAM025.ZIP (17 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins Download
TQFP (PFC) 80 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos