Product details

Function Differential, Fanout, Level translator Additive RMS jitter (typ) (fs) 30 Output frequency (max) (MHz) 400 Number of outputs 8 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features PCIe Gen 5 Compliant Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
Function Differential, Fanout, Level translator Additive RMS jitter (typ) (fs) 30 Output frequency (max) (MHz) 400 Number of outputs 8 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features PCIe Gen 5 Compliant Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
WQFN (RTA) 40 36 mm² 6 x 6
  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 400 MHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10-MHz to 40-MHz Crystal or Single-Ended Clock
  • Two Banks With 4 Differential Outputs Each
    • HCSL, or Hi-Z (Selectable per Bank)
    • Additive RMS Phase Jitter for PCIe Gen5 at 100 MHz:
      • 15 fs RMS (Typical)
  • –72 dBc at 156.25 MHz
  • LVCMOS Output With Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 40-lead WQFN (6 mm × 6 mm)
  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 400 MHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10-MHz to 40-MHz Crystal or Single-Ended Clock
  • Two Banks With 4 Differential Outputs Each
    • HCSL, or Hi-Z (Selectable per Bank)
    • Additive RMS Phase Jitter for PCIe Gen5 at 100 MHz:
      • 15 fs RMS (Typical)
  • –72 dBc at 156.25 MHz
  • LVCMOS Output With Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 40-lead WQFN (6 mm × 6 mm)

The LMK00338 device is an 8-output PCIe Gen1/Gen2/Gen3/Gen4/Gen5 fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 4 HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00338 operates from a 3.3-V core supply and 3 independent 3.3-V or 2.5-V output supplies.

The LMK00338 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

The LMK00338 device is an 8-output PCIe Gen1/Gen2/Gen3/Gen4/Gen5 fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 4 HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00338 operates from a 3.3-V core supply and 3 independent 3.3-V or 2.5-V output supplies.

The LMK00338 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

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Technical documentation

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Type Title Date
* Data sheet LMK00338 8-Output PCIe Gen1/Gen2/Gen3/Gen4/Gen5 Clock Buffer and Level Translator datasheet (Rev. C) PDF | HTML 12 Jul 2021
Application note Clocking for PCIe Applications PDF | HTML 28 Nov 2023
EVM User's guide LMK00338EVM User's Guide 13 Dec 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK00338EVM — LMK00338 PCIe Gen1/2/3 Clock Buffer Evaluation Module

The LMK00338 is a 400MHz, 8-output HCSL buffer intended for PCIe Gen1/2/3 Applications, low additive jitter clock distribution and level translation. The EVM allows the user to verify the functionality and performance specification of the device. Refer to the LMK00338 datasheet for the functional (...)

User guide: PDF
Not available on TI.com
Simulation model

LMK00338 IBIS Model

SNAM161.ZIP (107 KB) - IBIS Model
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design tool

PLLATINUMSIM-SW PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

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Hardware development
Evaluation board
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IDE, configuration, compiler or debugger
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