Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.5 GHz VCO  - LMK04806

LMK04806 (ACTIVE)

Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.5 GHz VCO

Recommended alternative parts

  • LMK04803  -  Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 1.9 GHz VCO
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  • LMK04808  -  Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.9 GHz VCO
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Description

The LMK04800 family is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.

The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

Features

  • Ultra-Low RMS Jitter Performance
    • 111 fs RMS Jitter (12 kHz to 20 MHz)
    • 123 fs RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum PLL Architecture
  • PLL1
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover Mode When Input Clocks are Lost
    • Automatic or Manual Triggering/Recovery
  • PLL2
    • Normalized PLL Noise Floor of -227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO
  • 2 Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50% Duty Cycle Output Divides, 1 to 1045 (Even and Odd)
  • LVPECL, LVDS, or LVCMOS Programmable Outputs
  • Digital Delay: Fixed or Dynamically Adjustable
  • 25 ps Step Analog Delay Control.
  • 14 Differential Outputs. Up to 26 Single Ended.
    • Up to 6 VCXO/Crystal Buffered Outputs
  • Clock Rates of up to 1536 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: -40 to 85 °C
  • 3.15 V to 3.45 V Operation
  • Package: 64-Pin WQFN (9.0 x 9.0 x 0.8 mm)

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Parametrics Compare all products in Dual / Cascaded PLL

 
Input Level
Output Level
Output Frequency (Min) (MHz)
Output Frequency (Max) (MHz)
No. of Outputs
Divider Ratio
Operating Temperature Range (C)
Supply Voltage (Min) (V)
Supply Voltage (Max) (V)
VCO Frequency (Min) (MHz)
VCO Frequency (Max) (MHz)
Pin/Package
RMS Jitter
Approx. Price (US$)
Special Features
LMK04806 LMK04803 LMK04805 LMK04808 LMK04906
LVPECL
LVDS
LVCMOS    
LVPECL
LVDS
LVCMOS    
LVPECL
LVDS
LVCMOS    
LVPECL
LVDS
LVCMOS    
LVCMOS
LVDS
LVPECL    
LVCMOS
LVPECL
LVDS    
LVCMOS
LVPECL
LVDS    
LVCMOS
LVPECL
LVDS    
LVCMOS
LVPECL
LVDS    
LVCMOS    
0.22     0.22     0.22     0.22     0.22    
2600     2030     2370     3072     2600    
14     14     14     14     6    
1 to 1045     1 to 1045     1 to 1045     1 to 1045     1 to 1045    
-40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85    
3.15     3.15     3.15     3.15     3.15    
3.45     3.45     3.45     3.45     3.45    
2370     1840     2148     2750     2370    
2600     2030     2370     3072     2600    
64WQFN     64WQFN     64WQFN     64WQFN     64WQFN    
0.111     0.111     0.111     0.111     0.1    
8.70 | 1ku     8.70 | 1ku     8.70 | 1ku     8.70 | 1ku     6.49 | 1ku    
3.3V Vcc/Vdd
Multiplier/Divider    
3.3V Vcc/Vdd
Multiplier/Divider    
3.3V Vcc/Vdd
Multiplier/Divider    
3.3V Vcc/Vdd
Multiplier/Divider    
Multiplier/Divider
3.3V Vcc/Vdd    
WEBENCH® Clock Architect - LMK04806
 
Input Frequency
 
MHz
Output Frequency
 
MHz
MHz
MHz
 
 

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