LMK04808 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs and Integrated 2.9 GHz VCO | TI.com

LMK04808 (ACTIVE)

Low-Noise Clock Jitter Cleaner with Dual Loop PLLs and Integrated 2.9 GHz VCO

Low-Noise Clock Jitter Cleaner with Dual Loop PLLs and Integrated 2.9 GHz VCO - LMK04808
 

Recommended alternative parts

  • LMK04803  -  Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 1.9 GHz VCO
  • LMK04805  -  Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO
  • LMK04806  -  Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.5 GHz VCO
  • LMK04821  -  Ultra Low Jitter Synthesizer and Jitter Cleaner with JESD204B Support

Description

The LMK0480x family is the industry’s highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.

The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

Features

  • Ultra-Low RMS Jitter Performance
    • 111 fs RMS Jitter (12 kHz to 20 MHz)
    • 123 fs RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Integrated Low-Noise Crystal Oscillator
      Circuit
    • Holdover Mode when Input Clocks are Lost
    • Automatic or Manual Triggering/Recovery
  • PLL2
    • Normalized PLL Noise Floor of –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO
  • 2 Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50 % Duty Cycle Output Divides, 1 to 1045 (Even
    and Odd)
  • 12 LVPECL, LVDS, or LVCMOS Programmable
    Outputs
  • Digital Delay: Fixed or Dynamically Adjustable
  • 25 ps Step Analog Delay Control.
  • 14 Differential Outputs. Up to 26 Single Ended.
    • Up to 6 VCXO/Crystal Buffered Outputs
  • Clock Rates of up to 1536 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock
    Distribution
  • Industrial Temperature Range: –40 to 85°C
  • 3.15-V to 3.45-V Operation
  • 2 Dedicated Buffered/Divided OSCin Clocks
  • Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)

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Parametrics Compare all products in Dual / Cascaded PLL

 
Number of Outputs
Output Level
Output Frequency (Min) (MHz)
Output Frequency (Max) (MHz)
Number of Inputs
Input Level
RMS Jitter
VCO Frequency (Min) (MHz)
VCO Frequency (Max) (MHz)
Supply Voltage (Min) (V)
Supply Voltage (Max) (V)
Features
Operating Temperature Range (C)
Pin/Package
LMK04808 LMK04208 LMK04610 LMK04616 LMK04805 LMK04806 LMK04821 LMK04826 LMK04828 LMK04832 LMK04906
14     7     10     16     14     14     15     15     15     14     7    
LVCMOS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
HCSL
HSDS
LVDS
LVPECL    
HCSL
HSDS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
0.22     0.329     0.03     0.03     0.22     0.22     0.045     0.225     0.289     0.305     0.22    
3072     3072     2000     2000     2370     2600     2075     2505     3080     3250     2600    
2     2     2     4     2     2     3     3     3     3     3    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
  CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.111     0.111     0.065     0.065     0.111     0.111     0.091     0.089     0.088     0.047     0.1    
2750     2750     5800     5800     2148     2370     365     1840     2370     2495     2370    
3072     3072     6200     6200     2370     2600     2075     2505     3080     3205     2600    
3.15     3.15     1.7     1.7     3.15     3.15     3.15     3.15     3.15     3.15     3.15    
3.45     3.45     3.465     3.465     3.45     3.45     3.45     3.45     3.45     3.45     3.45    
uWire
SPI
Holdover mode
Manual/auto switch
Int. xtal oscillator    
Holdover mode
Int. xtal oscillator
Manual/auto switch
SPI
uWire    
105C PCB temp
Holdover mode
JESD204B SYSREF
JESD204B SYSREF Generation
Jitter Cleaner/Clock Generator/Clock Distribution
Integrated LDOs
Integrated Loop Filters
Low Power Design
Manual and automatic switching between inputs
Semi-Digital PLL
SPI    
105C PCB temp
Holdover mode
JESD204B SYSREF
JESD204B SYSREF Generation
Jitter Cleaner/Clock Generator/Clock Distribution
Integrated LDOs
Integrated Loop Filters
Low Power Design
Manual and automatic switching between inputs
Semi-Digital PLL
SPI    
Holdover mode
Int. xtal oscillator
Manual/auto switch
SPI
uWire    
Holdover mode
Int. xtal oscillator
Manual/auto switch
SPI
uWire    
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
Holdover mode
JESD204B SYSREF Generation
Manual/auto switch
SPI    
Holdover mode
Int. xtal oscillator
Manual/auto switch
SPI
uWire    
-40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85