Ultra Low Jitter Synthesizer and Jitter Cleaner - LMK04828

LMK04828 (ACTIVE)

Ultra Low Jitter Synthesizer and Jitter Cleaner

Description

The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK0482x family ideal for providing flexible high performance clocking trees.

Features

  • JEDEC JESD204B Support
  • Ultra-Low RMS Jitter
    • 88 fs RMS Jitter (12 kHz to 20 MHz)
    • 91 fs RMS Jitter (100 Hz to 20 MHz)
    • –162.5 dBc/Hz Noise Floor at 245.76 MHz
  • Up to 14 Differential Device Clocks from PLL2
    • Up to 7 SYSREF Clocks
    • Maximum Clock Output Frequency 3.1 GHz
    • LVPECL, LVDS, HSDS, LCPECL
      Programmable Outputs from PLL2
  • Up to 1 Buffered VCXO/Crystal Output from PLL1
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Up to 3 Redundant Input Clocks
      • Automatic and Manual Switch-Over Modes
      • Hitless Switching and LOS
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover mode when Input Clocks are Lost
  • PLL2
    • Normalized [1 Hz] PLL Noise Floor of
      –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Two Integrated Low-Noise VCOs
  • 50% Duty Cycle Output Divides, 1 to 32
    (even and odd)
  • Precision Digital Delay, Dynamically Adjustable
  • 25 ps Step Analog Delay
  • Multi-mode: Dual PLL, single PLL, and Clock
    Distribution
  • Industrial Temperature Range: –40 to 85°C
  • Supports 105°C PCB Temperature (Measured at Thermal Pad)
  • 3.15-V to 3.45-V Operation
  • Package: 64-pin QFN (9.0 × 9.0 × 0.8 mm)

View more

Parametrics Compare all products in Dual / Cascaded PLL

 
No. of Outputs
Output Level
Output Frequency (Min) (MHz)
Output Frequency (Max) (MHz)
Number of Inputs
Input Level
RMS Jitter
VCO Frequency (Min) (MHz)
VCO Frequency (Max) (MHz)
Supply Voltage (Min) (V)
Supply Voltage (Max) (V)
Special Features
Operating Temperature Range (C)
Pin/Package
Approx. Price (US$)
LMK04828 LMK04821 LMK04826
15     15     15    
HSDS
LVCMOS
LVDS
LVPECL    
HSDS
LVCMOS
LVDS
LVPECL    
HSDS
LVCMOS
LVDS
LVPECL    
0.289     0.045     0.225    
3080     2075     2505    
3     3     3    
LVCMOS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
0.088     0.091     0.089    
2370     365     1840    
3080     2075     2505    
3.15     3.15     3.15    
3.45     3.45     3.45    
Design Tool Available
JESD204B
Jitter Cleaner    
Design Tool Available
JESD204B
Jitter Cleaner    
Design Tool Available
JESD204B
Jitter Cleaner    
-40 to 85     -40 to 85     -40 to 85    
64WQFN     64WQFN     64WQFN    
11.20 | 1ku     11.20 | 1ku     11.20 | 1ku