Ultra Low Jitter Synthesizer and Jitter Cleaner - LMK04828

LMK04828 (ACTIVE)

Ultra Low Jitter Synthesizer and Jitter Cleaner

Recommended alternative parts

  • LMK04826  -  Clock Jitter Cleaner w Dual Loop PLLs & JESD204B support

Description

The LMK04820 family is the industry's highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can individually be configured as a high performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, glitchless analog delay make the LMK04820 family ideal for providing flexible high performance clocking trees.

Features

  • JEDEC JESD204B Support
  • Ultra-Low RMS Jitter and Performance
    • 88 fs RMS jitter (12 kHz to 20 MHz)
    • 91 fs RMS jitter (100 Hz to 20 MHz)
    • –162.5 dBc/Hz noise floor at 245.76 MHz
  • Up to 14 Differential Device Clocks from PLL2
    • Up to 7 SYSREF Clocks
    • Maximum clock output frequency 3.1 GHz
    • LVPECL, LVDS, HSDS, LCPECL programmable outputs from PLL2
  • Up to 1 buffered VCXO/Crystal output from PLL1
    • LVPECL, LVDS, 2xLVCMOS programmable
  • Dual Loop PLLatinum PLL Architecture
  • PLL1
    • Up to 3 redundant input clocks
      • Automatic and manual switch-over modes
      • Hitless switching and LOS
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover mode when input clocks are lost
  • PLL2
    • Normalized [1 Hz] PLL noise floor of
      –227 dBc/Hz
    • Phase detector rate up to 155 MHz
    • OSCin frequency-doubler
    • Two Integrated Low-Noise VCOs
  • 50% duty cycle output divides, 1 to 32 (even and odd)
  • Precision digital delay, dynamically adjustable
  • 25 ps step analog delay
  • Multi-mode: Dual PLL, single PLL, and clock
    distribution in 0 delay option
  • Industrial Temperature Range: –40 to 85°C
  • 3.15 V to 3.45 V operation
  • Package: 64-pin QFN (9.0 × 9.0 × 0.8 mm)

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Parametrics Compare all products in Dual / Cascaded PLL

 
Input Level
Output Level
Output Frequency (Min) (MHz)
Output Frequency (Max) (MHz)
No. of Outputs
Divider Ratio
Supply Voltage (Min) (V)
Supply Voltage (Max) (V)
VCO Frequency (Min) (MHz)
VCO Frequency (Max) (MHz)
Pin/Package
RMS Jitter
Approx. Price (US$)
Special Features
LMK04828 LMK04826
LVPECL
LVDS
LVCMOS    
LVPECL
LVDS
LVCMOS    
LVCMOS
LVPECL
LVDS
HSDS    
LVCMOS
LVPECL
LVDS
HSDS    
0.3     0.3    
3100     2600    
15     15    
8 to 8191     8 to 8191    
3.1     3.1    
3.45     3.45    
2370     1785    
3005     2505    
64WQFN     64WQFN    
0.088     0.088    
11.20 | 1ku     11.20 | 1ku    
3.3V Vcc/Vdd
Multiplier/Divider    
3.3V Vcc/Vdd
Multiplier/Divider    

Featured tools and software

WEBENCH® Clock Architect - LMK04828
 
Input Frequency
 
MHz
Output Frequency
 
MHz
MHz
MHz
 
 

What is Clock Architect?

Companion parts

Part # Name Product Family Comments
ADS42JB49   Dual 14-Bit, 250 MSPS, Analog-to-Digital Converter   ANALOG TO DIGITAL CONVERTER - HIGH SPEED ADC (>10MSPS)    Dual 14-bit 250MBPS ADC with JESD204B interface  
ADS42JB69   Dual 16-Bit 250MSPS ADC with JESD204B Interface   ANALOG TO DIGITAL CONVERTER - HIGH SPEED ADC (>10MSPS)    Dual 16-bit 250MBPS ADC with JESD204B interface  
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