LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop | TI.com

LMK04832 (ACTIVE)

Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop

 

Description

The LMK04832 is an ultra-high performance clock conditioner with JEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems.

The LMK04832 can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover make the LMK04832 ideal for providing flexible high performance clocking trees.

Features

  • Maximum Clock Output Frequency: 3255 MHz
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Ultra-Low Noise, at 2500 MHz:
    • 54 fs RMS Jitter (12 kHz to 20 MHz)
    • 64 fs RMS Jitter (100 Hz to 20 MHz)
    • –157.6 dBc/Hz Noise Floor
  • Ultra-Low Noise, at 3200 MHz:
    • 61 fs RMS Jitter (12 kHz to 20 MHz)
    • 67 fs RMS Jitter (100 Hz to 100 MHz)
    • –156.5 dBc/Hz Noise Floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase Detector Rate up to 320 MHz
    • Two Integrated VCOs: 2440 to 2580 MHz
      and 2945 to 3255 MHz
  • Up to 14 Differential Device Clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS Programmable Outputs
  • Up to 1 Buffered VCXO/XO Output
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • 1-1023 CLKout Divider
  • 1-8191 SYSREF Divider
  • 25-ps Step Analog Delay for SYSREF Clocks
  • Digital Delay and Dynamic Digital Delay for Device Clock and SYSREF
  • Holdover Mode With PLL1
  • 0-Delay with PLL1 or PLL2
  • Supports 105°C PCB Temperature
    (Measured at Thermal Pad)

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Parametrics Compare all products in Dual/cascaded PLL

 
Number of outputs
Output level
Output frequency (Min) (MHz)
Output frequency (Max) (MHz)
Number of Inputs
Input level
RMS jitter
VCO frequency (Min) (MHz)
VCO frequency (Max) (MHz)
Supply Voltage (Min) (V)
Supply Voltage (Max) (V)
Features
Operating temperature range (C)
LMK04832 LMK04616 LMK04808 LMK04821 LMK04826 LMK04828
14     16     14     15     15     15    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
HCSL
HSDS
LVDS
LVPECL    
LVCMOS
LVDS
LVPECL    
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.305     0.03     0.22     0.045     0.225     0.289    
3250     2000     3072     2075     2505     3080    
3     4     2     3     3     3    
  CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
CML
HSDS
LCPECL
LVCMOS
LVDS
LVPECL    
0.047     0.065     0.111     0.091     0.089     0.088    
2495     5800     2750     365     1840     2370    
3205     6200     3072     2075     2505     3080    
3.15     1.7     3.15     3.15     3.15     3.15    
3.45     3.465     3.45     3.45     3.45     3.45    
Holdover mode
JESD204B SYSREF Generation
Manual/auto switch
SPI    
105C PCB temp
Holdover mode
JESD204B SYSREF
JESD204B SYSREF Generation
Jitter Cleaner/Clock Generator/Clock Distribution
Integrated LDOs
Integrated Loop Filters
Low Power Design
Manual and automatic switching between inputs
Semi-Digital PLL
SPI    
uWire
SPI
Holdover mode
Manual/auto switch
Int. xtal oscillator    
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
105C PCB temp
Holdover mode
Int. xtal oscillator
JESD204B SYSREF Generation
Manual/auto switch
SPI
uWire    
-40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85