The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The devices low jitter and high PSNR reduce bit error rates (BER) in high-speed serial links.
The device has two PLL channels and generates up to eight output clocks with 150-fs RMS jitter. Each PLL domain can select from any four reference inputs to synchronize its outputs.
Each PLL channel supports programmable loop bandwidth for jitter and wander attenuation and fractional frequency translation for flexible frequency configuration. Synchronization options supported on each PLL channel includes hitless switching with phase cancellation, digital holdover, DCO mode with <1 ppt/step for precise clock steering (IEEE 1588 PTP slave), and zero-delay mode for deterministic input-to-output phase offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.
The device can use a low-frequency TCXO/OCXO to determine the free-run or holdover frequency stability to maintain standards-compliant synchronization during LOR, or a standard XO when holdover frequency stability and wander are not critical. The device is fully programmable through I2C or SPI interface and supports custom frequency configuration on power-up with the internal EEPROM or ROM. The EEPROM is factory pre-programmable and in-system programmable.
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|Number of Inputs|
|Number of Outputs|
|Input Frequency (Min) (MHz)|
|Output Frequency (Min) (MHz)|
|VCC Core (V)|
|I/O Voltage (V)|
| ITU-T G.812 Type III,IV |
| 1.8 |
| EEPROM |