The LMK61E0 family of ultra-low jitter PLLatinumTM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I2C serial interface. The device provides fine and coarse frequency margining control through I2C serial interface, making it a digitally-controlled oscillator (DCXO).
The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.
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|Output Frequency (Max) (MHz)|
|VCC Core (V)|
|Operating Temperature Range (C)|
|Programmable with EEPROM||Standard||Standard||Standard||Programmable with EEPROM||Standard||Standard||Standard|
|LVCMOS||LVPECL||LVPECL||LVDS|| HCSL |
|-40 to 85||-40 to 85||-40 to 85||-40 to 85||-40 to 85||-40 to 85||-40 to 85||-40 to 85||-40 to 85||-40 to 85||-40 to 85||-40 to 85||-40 to 85||-40 to 85|
|Order Now||Samples Not Available||Order Now||Order Now||Order Now||Order Now||Order Now||Order Now||Samples Not Available||Samples Not Available||Samples Not Available||Samples Not Available||Samples Not Available||Order Now|