LP2997

ACTIVE

DDR-II Termination Regulator

Product details

Vin (min) (V) 1.8 Vin (max) (V) 5.5 Vout (min) (V) 0.822 Vout (max) (V) 0.887 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) 0 to 125 Product type DDR DDR memory type DDR2
Vin (min) (V) 1.8 Vin (max) (V) 5.5 Vout (min) (V) 0.822 Vout (max) (V) 0.887 Features Shutdown Pin for S3 Iq (typ) (mA) 0.32 Rating Catalog Operating temperature range (°C) 0 to 125 Product type DDR DDR memory type DDR2
HSOIC (DDA) 8 29.4 mm² 4.9 x 6 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • Available in SOIC-8, SO PowerPAD-8 Packages

All trademarks are the property of their respective owners.

  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • Available in SOIC-8, SO PowerPAD-8 Packages

All trademarks are the property of their respective owners.

The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 500mA continuous current and transient peaks up to 900mA in the application as required for DDR-II SDRAM termination. The LP2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2997 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 500mA continuous current and transient peaks up to 900mA in the application as required for DDR-II SDRAM termination. The LP2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2997 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

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Technical documentation

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Type Title Date
* Data sheet LP2997 DDR-II Termination Regulator datasheet (Rev. F) 04 Apr 2013
Application note Limiting DDR Termination Regulators’ Inrush Current 23 Aug 2016
Application note AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) 06 May 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

LP2997 PSpice Transient Model

SNVMAH7.ZIP (70 KB) - PSpice Model
Simulation model

LP2997 Unencrypted PSpice Transient Model

SNVMAH8.ZIP (4 KB) - PSpice Model
Reference designs

TIDA-010011 — High efficiency power supply architecture reference design for protection relay processor module

This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
HSOIC (DDA) 8 View options
SOIC (D) 8 View options

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