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PCA9306-Q1

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Automotive 2-bit bidirectional 400-kHz I2C/SMBus voltage level translator

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Data sheet

PCA9306-Q1

ACTIVE
Data sheet Order now

Product details

Features Enable pin Protocols I2C Frequency (max) (MHz) 0.4 VCCA (min) (V) 1.2 VCCA (max) (V) 5.5 VCCB (min) (V) 1.8 VCCB (max) (V) 5.5 Supply restrictions VCCA <= VCCB Rating Automotive Operating temperature range (°C) -40 to 105
Features Enable pin Protocols I2C Frequency (max) (MHz) 0.4 VCCA (min) (V) 1.2 VCCA (max) (V) 5.5 VCCB (min) (V) 1.8 VCCB (max) (V) 5.5 Supply restrictions VCCA <= VCCB Rating Automotive Operating temperature range (°C) -40 to 105
VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 2: –40°C to 105°C, TA
    • HBM ESD classification level H2
    • CDM ESD classification level C4B
  • 2-Bit bidirectional translator for SDA and SCL lines in mixed-mode I2C applications
  • Compatible with I2C and SMBus
  • Less than 1.5-ns maximum propagation delay to accommodate standard-mode and fast-mode I2C devices and multiple controllers
  • Allows voltage-level translation between
    • 1.2-V VREF1 and 1.8-V, 2.5-V, 3.3-V, or 5-V VREF2
    • 1.8-V VREF1 and 2.5-V, 3.3-V, or 5-V VREF2
    • 2.5-V VREF1 and 3.3-V, or 5-V VREF2
    • 3.3-V VREF1 and 5-V VREF2
  • Provides bidirectional voltage translation with no direction pin
  • Low 3.5-Ω ON-state connection between input and output ports provides less signal distortion
  • Open-drain I2C I/O Ports (SCL1, SDA1, SCL2, and SDA2)
  • 5-V tolerant I2C I/O ports to support mixed-mode signal operation
  • High-impedance SCL1, SDA1, SCL2, and SDA2 pins for EN = low
  • Lock-up-free operation for isolation when EN = Low
  • Flow-through pinout for ease of printed-circuit board trace routing
  • Latch-up performance exceeds 100 mA Per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-body model (A114-A)
    • 200-V Machine model (A115-A)
    • 1000-V Charged-device model (C101)
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 2: –40°C to 105°C, TA
    • HBM ESD classification level H2
    • CDM ESD classification level C4B
  • 2-Bit bidirectional translator for SDA and SCL lines in mixed-mode I2C applications
  • Compatible with I2C and SMBus
  • Less than 1.5-ns maximum propagation delay to accommodate standard-mode and fast-mode I2C devices and multiple controllers
  • Allows voltage-level translation between
    • 1.2-V VREF1 and 1.8-V, 2.5-V, 3.3-V, or 5-V VREF2
    • 1.8-V VREF1 and 2.5-V, 3.3-V, or 5-V VREF2
    • 2.5-V VREF1 and 3.3-V, or 5-V VREF2
    • 3.3-V VREF1 and 5-V VREF2
  • Provides bidirectional voltage translation with no direction pin
  • Low 3.5-Ω ON-state connection between input and output ports provides less signal distortion
  • Open-drain I2C I/O Ports (SCL1, SDA1, SCL2, and SDA2)
  • 5-V tolerant I2C I/O ports to support mixed-mode signal operation
  • High-impedance SCL1, SDA1, SCL2, and SDA2 pins for EN = low
  • Lock-up-free operation for isolation when EN = Low
  • Flow-through pinout for ease of printed-circuit board trace routing
  • Latch-up performance exceeds 100 mA Per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-body model (A114-A)
    • 200-V Machine model (A115-A)
    • 1000-V Charged-device model (C101)

This dual bidirectional I2C and SMBus voltage-level translator, with an enable (EN) input, is operational from 1.2-V to 3.3-V VREF1 and 1.8-V to 5.5-V VREF2.

The PCA9306-Q1 allows bidirectional voltage translations between 1.2 V and 5 V, without the use of a direction pin. The low ON-state resistance (ron) of the switch allows connections to be made with minimal propagation delay. When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and a high-impedance state exists between ports.

This dual bidirectional I2C and SMBus voltage-level translator, with an enable (EN) input, is operational from 1.2-V to 3.3-V VREF1 and 1.8-V to 5.5-V VREF2.

The PCA9306-Q1 allows bidirectional voltage translations between 1.2 V and 5 V, without the use of a direction pin. The low ON-state resistance (ron) of the switch allows connections to be made with minimal propagation delay. When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and a high-impedance state exists between ports.
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Technical documentation

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Type Title Date
* Data sheet PCA9306-Q1 Dual Bidirectional I2C Bus and SMBus Voltage-Level Translator datasheet (Rev. C) PDF | HTML 01 Apr 2022
Application brief Integrated vs. Discrete Open Drain Level Translation PDF | HTML 09 Jan 2024
Functional safety information PCA9306-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA PDF | HTML 02 Aug 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Choosing the Correct I2C Device for New Designs PDF | HTML 07 Sep 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Understanding the I2C Bus PDF | HTML 30 Jun 2015
Application note Maximum Clock Frequency of I2C Bus Using Repeaters 15 May 2015
Application note I2C Bus Pull-Up Resistor Calculation PDF | HTML 13 Feb 2015
Application note Programming Fun Lights With TI's TCA6507 30 Nov 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

PCA9306EVM — PCA9306 I2C translator evaluation module

This EVM can be used to evaluate the PCA9306 product in the DCU package. The I2C buses are easily accessed via SDA_1, SCL_1, SDA_2, and SCL_2 test points, and symmetrically laid out for optimal performance. All IC signals are available through test point connections.
User guide: PDF
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Simulation model

HSPICE MODEL OF PCA9306 (Rev. A)

SCEJ212A.ZIP (81 KB) - HSpice Model
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Simulation model

PCA9306 IBIS Model (Rev. A)

SCPM002A.ZIP (54 KB) - IBIS Model
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Design tool

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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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Reference designs

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This reference design provides a processing foundation for a cascaded imaging radar system. Cascade radar devices can support front, long-range (LRR) beam-forming applications as well as corner- and side-cascade radar and sensor fusion systems. This reference design provides qualified developers (...)
Design guide: PDF
Schematic: PDF
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The ADAS Sensor Interconnect Board is intended for applications where remote sensors like cameras, LIDAR or radar modules need to be connected to a central processing ECU. The board supports up to 3 coaxial and 1 LVDS twisted pair data inputs as well as 3 FMC cable and 1 board to board connector as (...)
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Schematic: PDF
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